9eac6d0a4e
This patch makes the various mach dirs that use the plat-orion GPIO code pass in GPIO-related platform info (GPIO controller base address, secondary base IRQ number, etc) explicitly, instead of having plat-orion get those values by including a mach dir include file -- the latter mechanism is problematic if you want to support multiple ARM platforms in the same kernel image. Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
45 lines
1.4 KiB
C
45 lines
1.4 KiB
C
/*
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* arch/arm/mach-mv78xx0/irq.c
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*
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* MV78xx0 IRQ handling.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <asm/gpio.h>
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#include <mach/bridge-regs.h>
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#include <plat/irq.h>
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#include "common.h"
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static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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BUG_ON(irq < IRQ_MV78XX0_GPIO_0_7 || irq > IRQ_MV78XX0_GPIO_24_31);
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orion_gpio_irq_handler((irq - IRQ_MV78XX0_GPIO_0_7) << 3);
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}
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void __init mv78xx0_init_irq(void)
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{
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orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
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orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
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orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
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/*
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* Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask
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* registers for core #1 are at an offset of 0x18 from those of
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* core #0.)
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*/
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orion_gpio_init(0, 32, GPIO_VIRT_BASE,
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mv78xx0_core_index() ? 0x18 : 0,
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IRQ_MV78XX0_GPIO_START);
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set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
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set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
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set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
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set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler);
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}
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