Paul Burton 4dd8ee5db1 MIPS: Add CP0 CMGCRBase definitions & accessor ... The CMGCRBase register is defined by the PRA specification as an optional register which indicates the physical base of the MIPS Coherence Manager Global Control Register block. This patch simply adds a definition for the base address field within the register, along with an accessor function for reading the register. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6356/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2014-03-06 21:25:22 +01:00
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asm	MIPS: Add CP0 CMGCRBase definitions & accessor	2014-03-06 21:25:22 +01:00
uapi/asm	MIPS: Wire up sched_setattr/sched_getattr syscalls	2014-02-04 13:47:46 +01:00