e9b7086b80
Commit a66cb3454f (ARM: OMAP: Map SRAM
later on with ioremap_exec()) moved the SRAM init to happen later
to remove a dependency to early SoC detection for map_io.
This broke booting on some boards not using Kconfig option for
OMAP_CLOCKS_SET_BY_BOOTLOADER as the dpll1 reprogramming would
cause the following error:
kernel BUG at arch/arm/plat-omap/sram.c:226!
Internal error: Oops - undefined instruction: 0 [#1] PREEMPT
Modules linked in:
CPU: 0 Not tainted (3.2.0-rc1-e3 #9)
PC is at omap_sram_reprogram_clock+0x28/0x30
LR is at omap1_select_table_rate+0x88/0xb4
pc : [<c001b0c4>] lr : [<c0019f54>] psr: 600000d3
sp : c035bf10 ip : c035bf20 fp : c035bf1c
r10: c035bfd4 r9 : 54029252 r8 : c03f8120
r7 : c0362b50 r6 : 00b71b00 r5 : c03873cc r4 : c0362b40
r3 : 00000000 r2 : c0362b40 r1 : 0000010a r0 : 00002cb0
Flags: nZCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel
Control: 0000317f Table: 10004000 DAC: 00000017
Process swapper (pid: 0, stack limit = 0xc035a270)
Stack: (0xc035bf10 to 0xc035c000)
bf00: c035bf3c c035bf20 c0019f54 c001b0ac
bf20: 00001000 00002cb3 00000004 c035ed4c c035bf74 c035bf40 c033ea24 c0019edc
bf40: c02f526c 00000002 00000015 bc058c9b 93111a16 c035335c 02000000 c035ed4c
bf60: c035ed4c c03f8120 c035bf84 c035bf78 c00194c4 c033e8ec c035bfc4 c035bf88
bf80: c033bc24 c00194a0 c035bf90 c035bf98 00000000 00000000 00000000 00000000
bfa0: 00000001 00000000 c0354678 c035ece4 10004000 103532f4 c035bff4 c035bfc8
bfc0: c0338574 c033b598 00000000 00000000 00000000 c035467c 0000317d c035c03c
bfe0: c0354678 c035ece4 00000000 c035bff8 10008040 c0338508 00000000 00000000
Backtrace:
[<c001b09c>] (omap_sram_reprogram_clock+0x0/0x30) from [<c0019f54>] (omap1_select_table_rate+0x88/0xb4)
[<c0019ecc>] (omap1_select_table_rate+0x0/0xb4) from [<c033ea24>] (omap1_clk_init+0x148/0x334)
r7:c035ed4c r6:00000004 r5:00002cb3 r4:00001000
[<c033e8dc>] (omap1_clk_init+0x0/0x334) from [<c00194c4>] (omap1_init_early+0x34/0x48)
r8:c03f8120 r7:c035ed4c r6:c035ed4c r5:02000000 r4:c035335c
[<c0019490>] (omap1_init_early+0x0/0x48) from [<c033bc24>] (setup_arch+0x69c/0x79c)
[<c033b588>] (setup_arch+0x0/0x79c) from [<c0338574>] (start_kernel+0x7c/0x2f4)
[<c03384f8>] (start_kernel+0x0/0x2f4) from [<10008040>] (0x10008040)
r7:c035ece4 r6:c0354678 r5:c035c03c r4:0000317d
Code: 0a000002 e1a0e00f e12fff13 e89da800 (e7f001f2)
Fix this by adding omap1_clk_late_init() that only reprograms dpll1
if the bootloader rate is less than 60MHz. This also allows removing
of the OMAP_CLOCKS_SET_BY_BOOTLOADER option.
Reported-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Tony Lindgren <tony@atomide.com>
114 lines
3.8 KiB
C
114 lines
3.8 KiB
C
/*
|
|
* linux/arch/arm/mach-omap1/clock.h
|
|
*
|
|
* Copyright (C) 2004 - 2005, 2009 Nokia corporation
|
|
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
|
|
* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
|
|
#define __ARCH_ARM_MACH_OMAP1_CLOCK_H
|
|
|
|
#include <linux/clk.h>
|
|
|
|
#include <plat/clock.h>
|
|
|
|
int omap1_clk_init(void);
|
|
void omap1_clk_late_init(void);
|
|
extern int omap1_clk_enable(struct clk *clk);
|
|
extern void omap1_clk_disable(struct clk *clk);
|
|
extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
|
|
extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate);
|
|
extern unsigned long omap1_ckctl_recalc(struct clk *clk);
|
|
extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
|
|
extern unsigned long omap1_sossi_recalc(struct clk *clk);
|
|
extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
|
|
extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate);
|
|
extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate);
|
|
extern unsigned long omap1_uart_recalc(struct clk *clk);
|
|
extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate);
|
|
extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate);
|
|
extern void omap1_init_ext_clk(struct clk *clk);
|
|
extern int omap1_select_table_rate(struct clk *clk, unsigned long rate);
|
|
extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate);
|
|
extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
|
|
extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
|
|
extern unsigned long omap1_watchdog_recalc(struct clk *clk);
|
|
|
|
#ifdef CONFIG_OMAP_RESET_CLOCKS
|
|
extern void omap1_clk_disable_unused(struct clk *clk);
|
|
#else
|
|
#define omap1_clk_disable_unused NULL
|
|
#endif
|
|
|
|
struct uart_clk {
|
|
struct clk clk;
|
|
unsigned long sysc_addr;
|
|
};
|
|
|
|
/* Provide a method for preventing idling some ARM IDLECT clocks */
|
|
struct arm_idlect1_clk {
|
|
struct clk clk;
|
|
unsigned long no_idle_count;
|
|
__u8 idlect_shift;
|
|
};
|
|
|
|
/* ARM_CKCTL bit shifts */
|
|
#define CKCTL_PERDIV_OFFSET 0
|
|
#define CKCTL_LCDDIV_OFFSET 2
|
|
#define CKCTL_ARMDIV_OFFSET 4
|
|
#define CKCTL_DSPDIV_OFFSET 6
|
|
#define CKCTL_TCDIV_OFFSET 8
|
|
#define CKCTL_DSPMMUDIV_OFFSET 10
|
|
/*#define ARM_TIMXO 12*/
|
|
#define EN_DSPCK 13
|
|
/*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
|
|
/* DSP_CKCTL bit shifts */
|
|
#define CKCTL_DSPPERDIV_OFFSET 0
|
|
|
|
/* ARM_IDLECT2 bit shifts */
|
|
#define EN_WDTCK 0
|
|
#define EN_XORPCK 1
|
|
#define EN_PERCK 2
|
|
#define EN_LCDCK 3
|
|
#define EN_LBCK 4 /* Not on 1610/1710 */
|
|
/*#define EN_HSABCK 5*/
|
|
#define EN_APICK 6
|
|
#define EN_TIMCK 7
|
|
#define DMACK_REQ 8
|
|
#define EN_GPIOCK 9 /* Not on 1610/1710 */
|
|
/*#define EN_LBFREECK 10*/
|
|
#define EN_CKOUT_ARM 11
|
|
|
|
/* ARM_IDLECT3 bit shifts */
|
|
#define EN_OCPI_CK 0
|
|
#define EN_TC1_CK 2
|
|
#define EN_TC2_CK 4
|
|
|
|
/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
|
|
#define EN_DSPTIMCK 5
|
|
|
|
/* Various register defines for clock controls scattered around OMAP chip */
|
|
#define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */
|
|
#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
|
|
#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
|
|
#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
|
|
#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
|
|
#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
|
|
#define COM_CLK_DIV_CTRL_SEL 0xfffe0878
|
|
#define SOFT_REQ_REG 0xfffe0834
|
|
#define SOFT_REQ_REG2 0xfffe0880
|
|
|
|
extern __u32 arm_idlect1_mask;
|
|
extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
|
|
|
|
extern const struct clkops clkops_dspck;
|
|
extern const struct clkops clkops_dummy;
|
|
extern const struct clkops clkops_uart_16xx;
|
|
extern const struct clkops clkops_generic;
|
|
|
|
#endif
|