8fd524b355
This kills bad_dma_address variable, the old mechanism to enable IOMMU drivers to make dma_mapping_error() work in IOMMU's specific way. bad_dma_address variable was introduced to enable IOMMU drivers to make dma_mapping_error() work in IOMMU's specific way. However, it can't handle systems that use both swiotlb and HW IOMMU. SO we introduced dma_map_ops->mapping_error to solve that case. Intel VT-d, GART, and swiotlb already use dma_map_ops->mapping_error. Calgary, AMD IOMMU, and nommu use zero for an error dma address. This adds DMA_ERROR_CODE and converts them to use it (as SPARC and POWER does). Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: muli@il.ibm.com Cc: joerg.roedel@amd.com LKML-Reference: <1258287594-8777-3-git-send-email-fujita.tomonori@lab.ntt.co.jp> Signed-off-by: Ingo Molnar <mingo@elte.hu>
165 lines
3.8 KiB
C
165 lines
3.8 KiB
C
#ifndef _ASM_X86_DMA_MAPPING_H
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#define _ASM_X86_DMA_MAPPING_H
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/*
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* IOMMU interface. See Documentation/PCI/PCI-DMA-mapping.txt and
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* Documentation/DMA-API.txt for documentation.
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*/
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#include <linux/kmemcheck.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-debug.h>
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#include <linux/dma-attrs.h>
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#include <asm/io.h>
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#include <asm/swiotlb.h>
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#include <asm-generic/dma-coherent.h>
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#ifdef CONFIG_ISA
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# define ISA_DMA_BIT_MASK DMA_BIT_MASK(24)
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#else
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# define ISA_DMA_BIT_MASK DMA_BIT_MASK(32)
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#endif
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#define DMA_ERROR_CODE 0
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extern int iommu_merge;
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extern struct device x86_dma_fallback_dev;
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extern int panic_on_overflow;
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extern struct dma_map_ops *dma_ops;
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static inline struct dma_map_ops *get_dma_ops(struct device *dev)
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{
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#ifdef CONFIG_X86_32
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return dma_ops;
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#else
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if (unlikely(!dev) || !dev->archdata.dma_ops)
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return dma_ops;
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else
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return dev->archdata.dma_ops;
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#endif
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}
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#include <asm-generic/dma-mapping-common.h>
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/* Make sure we keep the same behaviour */
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static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
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{
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struct dma_map_ops *ops = get_dma_ops(dev);
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if (ops->mapping_error)
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return ops->mapping_error(dev, dma_addr);
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return (dma_addr == DMA_ERROR_CODE);
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}
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#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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#define dma_is_consistent(d, h) (1)
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extern int dma_supported(struct device *hwdev, u64 mask);
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extern int dma_set_mask(struct device *dev, u64 mask);
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extern void *dma_generic_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_addr, gfp_t flag);
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static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
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{
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if (!dev->dma_mask)
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return 0;
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return addr + size <= *dev->dma_mask;
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}
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static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
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{
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return paddr;
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}
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static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
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{
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return daddr;
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}
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static inline void
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dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction dir)
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{
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flush_write_buffers();
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}
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static inline int dma_get_cache_alignment(void)
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{
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/* no easy way to get cache size on all x86, so return the
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* maximum possible, to be safe */
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return boot_cpu_data.x86_clflush_size;
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}
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static inline unsigned long dma_alloc_coherent_mask(struct device *dev,
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gfp_t gfp)
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{
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unsigned long dma_mask = 0;
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dma_mask = dev->coherent_dma_mask;
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if (!dma_mask)
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dma_mask = (gfp & GFP_DMA) ? DMA_BIT_MASK(24) : DMA_BIT_MASK(32);
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return dma_mask;
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}
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static inline gfp_t dma_alloc_coherent_gfp_flags(struct device *dev, gfp_t gfp)
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{
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unsigned long dma_mask = dma_alloc_coherent_mask(dev, gfp);
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if (dma_mask <= DMA_BIT_MASK(24))
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gfp |= GFP_DMA;
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#ifdef CONFIG_X86_64
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if (dma_mask <= DMA_BIT_MASK(32) && !(gfp & GFP_DMA))
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gfp |= GFP_DMA32;
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#endif
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return gfp;
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}
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static inline void *
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dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
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gfp_t gfp)
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{
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struct dma_map_ops *ops = get_dma_ops(dev);
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void *memory;
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gfp &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
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if (dma_alloc_from_coherent(dev, size, dma_handle, &memory))
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return memory;
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if (!dev)
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dev = &x86_dma_fallback_dev;
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if (!is_device_dma_capable(dev))
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return NULL;
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if (!ops->alloc_coherent)
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return NULL;
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memory = ops->alloc_coherent(dev, size, dma_handle,
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dma_alloc_coherent_gfp_flags(dev, gfp));
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debug_dma_alloc_coherent(dev, size, *dma_handle, memory);
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return memory;
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}
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static inline void dma_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t bus)
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{
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struct dma_map_ops *ops = get_dma_ops(dev);
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WARN_ON(irqs_disabled()); /* for portability */
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if (dma_release_from_coherent(dev, get_order(size), vaddr))
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return;
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debug_dma_free_coherent(dev, size, vaddr, bus);
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if (ops->free_coherent)
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ops->free_coherent(dev, size, vaddr, bus);
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}
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#endif
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