4b3f686d4a
The patch below corrects multiple occurances of "the the" typos across several files, both in source comments and KConfig files. There is no actual code changed, only text. Note this only affects the /arch directory, and I believe I could find many more elsewhere. :) Signed-off-by: Adrian Bunk <bunk@stusta.de>
426 lines
10 KiB
C
426 lines
10 KiB
C
/* arch/arm/mach-lh7a40x/arch-lpd7a40x.c
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*
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* Copyright (C) 2004 Logic Product Development
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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*/
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#include <linux/tty.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/hardware.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include "common.h"
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#define CPLD_INT_NETHERNET (1<<0)
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#define CPLD_INTMASK_ETHERNET (1<<2)
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#if defined (CONFIG_MACH_LPD7A400)
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# define CPLD_INT_NTOUCH (1<<1)
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# define CPLD_INTMASK_TOUCH (1<<3)
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# define CPLD_INT_PEN (1<<4)
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# define CPLD_INTMASK_PEN (1<<4)
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# define CPLD_INT_PIRQ (1<<4)
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#endif
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#define CPLD_INTMASK_CPLD (1<<7)
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#define CPLD_INT_CPLD (1<<6)
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#define CPLD_CONTROL_SWINT (1<<7) /* Disable all CPLD IRQs */
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#define CPLD_CONTROL_OCMSK (1<<6) /* Mask USB1 connect IRQ */
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#define CPLD_CONTROL_PDRV (1<<5) /* PCC_nDRV high */
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#define CPLD_CONTROL_USB1C (1<<4) /* USB1 connect IRQ active */
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#define CPLD_CONTROL_USB1P (1<<3) /* USB1 power disable */
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#define CPLD_CONTROL_AWKP (1<<2) /* Auto-wakeup disabled */
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#define CPLD_CONTROL_LCD_ENABLE (1<<1) /* LCD Vee enable */
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#define CPLD_CONTROL_WRLAN_NENABLE (1<<0) /* SMC91x power disable */
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static struct resource smc91x_resources[] = {
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[0] = {
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.start = CPLD00_PHYS,
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.end = CPLD00_PHYS + CPLD00_SIZE - 1, /* Only needs 16B */
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_LPD7A40X_ETH_INT,
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.end = IRQ_LPD7A40X_ETH_INT,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device smc91x_device = {
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.name = "smc91x",
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.id = 0,
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.num_resources = ARRAY_SIZE(smc91x_resources),
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.resource = smc91x_resources,
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};
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static struct resource lh7a40x_usbclient_resources[] = {
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[0] = {
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.start = USB_PHYS,
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.end = (USB_PHYS + PAGE_SIZE),
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_USB,
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.end = IRQ_USB,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 lh7a40x_usbclient_dma_mask = 0xffffffffUL;
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static struct platform_device lh7a40x_usbclient_device = {
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// .name = "lh7a40x_udc",
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.name = "lh7-udc",
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.id = 0,
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.dev = {
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.dma_mask = &lh7a40x_usbclient_dma_mask,
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.coherent_dma_mask = 0xffffffffUL,
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},
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.num_resources = ARRAY_SIZE (lh7a40x_usbclient_resources),
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.resource = lh7a40x_usbclient_resources,
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};
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#if defined (CONFIG_ARCH_LH7A404)
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static struct resource lh7a404_usbhost_resources [] = {
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[0] = {
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.start = USBH_PHYS,
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.end = (USBH_PHYS + 0xFF),
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_USHINTR,
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.end = IRQ_USHINTR,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 lh7a404_usbhost_dma_mask = 0xffffffffUL;
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static struct platform_device lh7a404_usbhost_device = {
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.name = "lh7a404-ohci",
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.id = 0,
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.dev = {
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.dma_mask = &lh7a404_usbhost_dma_mask,
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.coherent_dma_mask = 0xffffffffUL,
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},
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.num_resources = ARRAY_SIZE (lh7a404_usbhost_resources),
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.resource = lh7a404_usbhost_resources,
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};
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#endif
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static struct platform_device* lpd7a40x_devs[] __initdata = {
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&smc91x_device,
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&lh7a40x_usbclient_device,
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#if defined (CONFIG_ARCH_LH7A404)
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&lh7a404_usbhost_device,
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#endif
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};
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extern void lpd7a400_map_io (void);
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static void __init lpd7a40x_init (void)
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{
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#if defined (CONFIG_MACH_LPD7A400)
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CPLD_CONTROL |= 0
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| CPLD_CONTROL_SWINT /* Disable software interrupt */
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| CPLD_CONTROL_OCMSK; /* Mask USB1 connection IRQ */
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CPLD_CONTROL &= ~(0
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| CPLD_CONTROL_LCD_ENABLE /* Disable LCD */
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| CPLD_CONTROL_WRLAN_NENABLE /* Enable SMC91x */
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);
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#endif
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#if defined (CONFIG_MACH_LPD7A404)
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CPLD_CONTROL &= ~(0
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| CPLD_CONTROL_WRLAN_NENABLE /* Enable SMC91x */
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);
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#endif
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platform_add_devices (lpd7a40x_devs, ARRAY_SIZE (lpd7a40x_devs));
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#if defined (CONFIG_FB_ARMCLCD)
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lh7a40x_clcd_init ();
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#endif
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}
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static void lh7a40x_ack_cpld_irq (u32 irq)
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{
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/* CPLD doesn't have ack capability, but some devices may */
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#if defined (CPLD_INTMASK_TOUCH)
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/* The touch control *must* mask the interrupt because the
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* interrupt bit is read by the driver to determine if the pen
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* is still down. */
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if (irq == IRQ_TOUCH)
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CPLD_INTERRUPTS |= CPLD_INTMASK_TOUCH;
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#endif
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}
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static void lh7a40x_mask_cpld_irq (u32 irq)
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{
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switch (irq) {
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case IRQ_LPD7A40X_ETH_INT:
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CPLD_INTERRUPTS |= CPLD_INTMASK_ETHERNET;
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break;
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#if defined (IRQ_TOUCH)
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case IRQ_TOUCH:
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CPLD_INTERRUPTS |= CPLD_INTMASK_TOUCH;
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break;
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#endif
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}
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}
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static void lh7a40x_unmask_cpld_irq (u32 irq)
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{
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switch (irq) {
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case IRQ_LPD7A40X_ETH_INT:
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CPLD_INTERRUPTS &= ~CPLD_INTMASK_ETHERNET;
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break;
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#if defined (IRQ_TOUCH)
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case IRQ_TOUCH:
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CPLD_INTERRUPTS &= ~CPLD_INTMASK_TOUCH;
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break;
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#endif
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}
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}
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static struct irq_chip lpd7a40x_cpld_chip = {
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.name = "CPLD",
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.ack = lh7a40x_ack_cpld_irq,
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.mask = lh7a40x_mask_cpld_irq,
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.unmask = lh7a40x_unmask_cpld_irq,
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};
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static void lpd7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc,
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struct pt_regs *regs)
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{
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unsigned int mask = CPLD_INTERRUPTS;
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desc->chip->ack (irq);
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if ((mask & (1<<0)) == 0) /* WLAN */
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IRQ_DISPATCH (IRQ_LPD7A40X_ETH_INT);
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#if defined (IRQ_TOUCH)
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if ((mask & (1<<1)) == 0) /* Touch */
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IRQ_DISPATCH (IRQ_TOUCH);
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#endif
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desc->chip->unmask (irq); /* Level-triggered need this */
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}
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void __init lh7a40x_init_board_irq (void)
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{
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int irq;
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/* Rev A (v2.8): PF0, PF1, PF2, and PF3 are available IRQs.
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PF7 supports the CPLD.
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Rev B (v3.4): PF0, PF1, and PF2 are available IRQs.
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PF3 supports the CPLD.
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(Some) LPD7A404 prerelease boards report a version
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number of 0x16, but we force an override since the
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hardware is of the newer variety.
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*/
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unsigned char cpld_version = CPLD_REVISION;
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int pinCPLD = (cpld_version == 0x28) ? 7 : 3;
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#if defined CONFIG_MACH_LPD7A404
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cpld_version = 0x34; /* Coerce LPD7A404 to RevB */
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#endif
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/* First, configure user controlled GPIOF interrupts */
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GPIO_PFDD &= ~0x0f; /* PF0-3 are inputs */
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GPIO_INTTYPE1 &= ~0x0f; /* PF0-3 are level triggered */
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GPIO_INTTYPE2 &= ~0x0f; /* PF0-3 are active low */
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barrier ();
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GPIO_GPIOFINTEN |= 0x0f; /* Enable PF0, PF1, PF2, and PF3 IRQs */
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/* Then, configure CPLD interrupt */
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/* Disable all CPLD interrupts */
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#if defined (CONFIG_MACH_LPD7A400)
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CPLD_INTERRUPTS = CPLD_INTMASK_TOUCH | CPLD_INTMASK_PEN
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| CPLD_INTMASK_ETHERNET;
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/* *** FIXME: don't know why we need 7 and 4. 7 is way wrong
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and 4 is uncefined. */
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// (1<<7)|(1<<4)|(1<<3)|(1<<2);
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#endif
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#if defined (CONFIG_MACH_LPD7A404)
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CPLD_INTERRUPTS = CPLD_INTMASK_ETHERNET;
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/* *** FIXME: don't know why we need 6 and 5, neither is defined. */
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// (1<<6)|(1<<5)|(1<<3);
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#endif
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GPIO_PFDD &= ~(1 << pinCPLD); /* Make input */
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GPIO_INTTYPE1 &= ~(1 << pinCPLD); /* Level triggered */
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GPIO_INTTYPE2 &= ~(1 << pinCPLD); /* Active low */
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barrier ();
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GPIO_GPIOFINTEN |= (1 << pinCPLD); /* Enable */
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/* Cascade CPLD interrupts */
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for (irq = IRQ_BOARD_START;
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irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
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set_irq_chip (irq, &lpd7a40x_cpld_chip);
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set_irq_handler (irq, do_level_IRQ);
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set_irq_flags (irq, IRQF_VALID);
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}
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set_irq_chained_handler ((cpld_version == 0x28)
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? IRQ_CPLD_V28
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: IRQ_CPLD_V34,
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lpd7a40x_cpld_handler);
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}
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static struct map_desc lpd7a40x_io_desc[] __initdata = {
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{
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.virtual = IO_VIRT,
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.pfn = __phys_to_pfn(IO_PHYS),
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.length = IO_SIZE,
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.type = MT_DEVICE
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},
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{ /* Mapping added to work around chip select problems */
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.virtual = IOBARRIER_VIRT,
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.pfn = __phys_to_pfn(IOBARRIER_PHYS),
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.length = IOBARRIER_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = CF_VIRT,
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.pfn = __phys_to_pfn(CF_PHYS),
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.length = CF_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = CPLD02_VIRT,
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.pfn = __phys_to_pfn(CPLD02_PHYS),
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.length = CPLD02_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = CPLD06_VIRT,
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.pfn = __phys_to_pfn(CPLD06_PHYS),
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.length = CPLD06_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = CPLD08_VIRT,
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.pfn = __phys_to_pfn(CPLD08_PHYS),
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.length = CPLD08_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = CPLD08_VIRT,
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.pfn = __phys_to_pfn(CPLD08_PHYS),
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.length = CPLD08_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = CPLD0A_VIRT,
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.pfn = __phys_to_pfn(CPLD0A_PHYS),
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.length = CPLD0A_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = CPLD0C_VIRT,
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.pfn = __phys_to_pfn(CPLD0C_PHYS),
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.length = CPLD0C_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = CPLD0E_VIRT,
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.pfn = __phys_to_pfn(CPLD0E_PHYS),
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.length = CPLD0E_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = CPLD10_VIRT,
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.pfn = __phys_to_pfn(CPLD10_PHYS),
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.length = CPLD10_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = CPLD12_VIRT,
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.pfn = __phys_to_pfn(CPLD12_PHYS),
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.length = CPLD12_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = CPLD14_VIRT,
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.pfn = __phys_to_pfn(CPLD14_PHYS),
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.length = CPLD14_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = CPLD16_VIRT,
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.pfn = __phys_to_pfn(CPLD16_PHYS),
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.length = CPLD16_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = CPLD18_VIRT,
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.pfn = __phys_to_pfn(CPLD18_PHYS),
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.length = CPLD18_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = CPLD1A_VIRT,
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.pfn = __phys_to_pfn(CPLD1A_PHYS),
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.length = CPLD1A_SIZE,
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.type = MT_DEVICE
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},
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};
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void __init
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lpd7a40x_map_io(void)
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{
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iotable_init (lpd7a40x_io_desc, ARRAY_SIZE (lpd7a40x_io_desc));
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}
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#ifdef CONFIG_MACH_LPD7A400
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MACHINE_START (LPD7A400, "Logic Product Development LPD7A400-10")
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/* Maintainer: Marc Singer */
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.phys_io = 0x80000000,
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.io_pg_offst = ((io_p2v (0x80000000))>>18) & 0xfffc,
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.boot_params = 0xc0000100,
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.map_io = lpd7a40x_map_io,
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.init_irq = lh7a400_init_irq,
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.timer = &lh7a40x_timer,
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.init_machine = lpd7a40x_init,
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MACHINE_END
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#endif
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#ifdef CONFIG_MACH_LPD7A404
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MACHINE_START (LPD7A404, "Logic Product Development LPD7A404-10")
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/* Maintainer: Marc Singer */
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.phys_io = 0x80000000,
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.io_pg_offst = ((io_p2v (0x80000000))>>18) & 0xfffc,
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.boot_params = 0xc0000100,
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.map_io = lpd7a40x_map_io,
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.init_irq = lh7a404_init_irq,
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.timer = &lh7a40x_timer,
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.init_machine = lpd7a40x_init,
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MACHINE_END
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#endif
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