d5663e7a40
Platform data is provided for two instance of pl330 DMAC, but only one DMAC is register with amba_device. This patch register the second instance. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
267 lines
5.8 KiB
C
267 lines
5.8 KiB
C
/* linux/arch/arm/mach-s5pc100/dma.c
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Copyright (C) 2010 Samsung Electronics Co. Ltd.
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* Jaswinder Singh <jassi.brar@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/pl330.h>
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#include <asm/irq.h>
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#include <plat/devs.h>
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#include <plat/irqs.h>
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#include <mach/map.h>
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#include <mach/irqs.h>
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#include <mach/dma.h>
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static u64 dma_dmamask = DMA_BIT_MASK(32);
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struct dma_pl330_peri pdma0_peri[30] = {
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{
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.peri_id = (u8)DMACH_UART0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_UART1_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_UART2_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART2_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_UART3_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART3_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = DMACH_IRDA,
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}, {
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.peri_id = (u8)DMACH_I2S0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_I2S0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_I2S0S_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_I2S1_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_I2S1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_I2S2_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_I2S2_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_SPI0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_SPI0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_SPI1_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_SPI1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_SPI2_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_SPI2_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_AC97_MICIN,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_AC97_PCMIN,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_AC97_PCMOUT,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_EXTERNAL,
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}, {
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.peri_id = (u8)DMACH_PWM,
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}, {
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.peri_id = (u8)DMACH_SPDIF,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_HSI_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_HSI_TX,
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.rqtype = MEMTODEV,
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},
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};
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struct dma_pl330_platdata s5pc100_pdma0_pdata = {
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.nr_valid_peri = ARRAY_SIZE(pdma0_peri),
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.peri = pdma0_peri,
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};
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struct amba_device s5pc100_device_pdma0 = {
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.dev = {
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.init_name = "dma-pl330.0",
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.dma_mask = &dma_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = &s5pc100_pdma0_pdata,
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},
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.res = {
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.start = S5PC100_PA_PDMA0,
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.end = S5PC100_PA_PDMA0 + SZ_4K,
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.flags = IORESOURCE_MEM,
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},
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.irq = {IRQ_PDMA0, NO_IRQ},
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.periphid = 0x00041330,
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};
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struct dma_pl330_peri pdma1_peri[30] = {
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{
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.peri_id = (u8)DMACH_UART0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_UART1_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_UART2_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART2_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_UART3_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART3_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = DMACH_IRDA,
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}, {
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.peri_id = (u8)DMACH_I2S0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_I2S0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_I2S0S_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_I2S1_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_I2S1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_I2S2_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_I2S2_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_SPI0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_SPI0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_SPI1_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_SPI1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_SPI2_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_SPI2_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_PCM0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_PCM1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_PCM1_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_PCM1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_MSM_REQ0,
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}, {
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.peri_id = (u8)DMACH_MSM_REQ1,
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}, {
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.peri_id = (u8)DMACH_MSM_REQ2,
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}, {
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.peri_id = (u8)DMACH_MSM_REQ3,
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},
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};
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struct dma_pl330_platdata s5pc100_pdma1_pdata = {
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.nr_valid_peri = ARRAY_SIZE(pdma1_peri),
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.peri = pdma1_peri,
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};
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struct amba_device s5pc100_device_pdma1 = {
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.dev = {
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.init_name = "dma-pl330.1",
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.dma_mask = &dma_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = &s5pc100_pdma1_pdata,
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},
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.res = {
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.start = S5PC100_PA_PDMA1,
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.end = S5PC100_PA_PDMA1 + SZ_4K,
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.flags = IORESOURCE_MEM,
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},
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.irq = {IRQ_PDMA1, NO_IRQ},
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.periphid = 0x00041330,
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};
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static int __init s5pc100_dma_init(void)
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{
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amba_device_register(&s5pc100_device_pdma0, &iomem_resource);
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amba_device_register(&s5pc100_device_pdma1, &iomem_resource);
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return 0;
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}
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arch_initcall(s5pc100_dma_init);
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