24f287e412
When the cpu count is high and contention hits an atomic object, the processors can synchronize such that some cpus continually get knocked out and cannot complete the atomic update. So implement an exponential backoff when SMP. Signed-off-by: David S. Miller <davem@davemloft.net>
164 lines
3.4 KiB
ArmAsm
164 lines
3.4 KiB
ArmAsm
/* atomic.S: These things are too big to do inline.
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*
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* Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
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*/
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#include <asm/asi.h>
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#include <asm/backoff.h>
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.text
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/* Two versions of the atomic routines, one that
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* does not return a value and does not perform
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* memory barriers, and a second which returns
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* a value and does the barriers.
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*/
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.globl atomic_add
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.type atomic_add,#function
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atomic_add: /* %o0 = increment, %o1 = atomic_ptr */
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BACKOFF_SETUP(%o2)
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1: lduw [%o1], %g1
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add %g1, %o0, %g7
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cas [%o1], %g1, %g7
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cmp %g1, %g7
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bne,pn %icc, 2f
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nop
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retl
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nop
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2: BACKOFF_SPIN(%o2, %o3, 1b)
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.size atomic_add, .-atomic_add
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.globl atomic_sub
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.type atomic_sub,#function
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atomic_sub: /* %o0 = decrement, %o1 = atomic_ptr */
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BACKOFF_SETUP(%o2)
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1: lduw [%o1], %g1
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sub %g1, %o0, %g7
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cas [%o1], %g1, %g7
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cmp %g1, %g7
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bne,pn %icc, 2f
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nop
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retl
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nop
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2: BACKOFF_SPIN(%o2, %o3, 1b)
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.size atomic_sub, .-atomic_sub
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/* On SMP we need to use memory barriers to ensure
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* correct memory operation ordering, nop these out
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* for uniprocessor.
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*/
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#ifdef CONFIG_SMP
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#define ATOMIC_PRE_BARRIER membar #StoreLoad | #LoadLoad;
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#define ATOMIC_POST_BARRIER \
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ba,pt %xcc, 80b; \
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membar #StoreLoad | #StoreStore
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80: retl
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nop
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#else
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#define ATOMIC_PRE_BARRIER
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#define ATOMIC_POST_BARRIER
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#endif
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.globl atomic_add_ret
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.type atomic_add_ret,#function
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atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
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BACKOFF_SETUP(%o2)
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ATOMIC_PRE_BARRIER
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1: lduw [%o1], %g1
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add %g1, %o0, %g7
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cas [%o1], %g1, %g7
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cmp %g1, %g7
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bne,pn %icc, 2f
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add %g7, %o0, %g7
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sra %g7, 0, %o0
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ATOMIC_POST_BARRIER
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retl
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nop
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2: BACKOFF_SPIN(%o2, %o3, 1b)
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.size atomic_add_ret, .-atomic_add_ret
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.globl atomic_sub_ret
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.type atomic_sub_ret,#function
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atomic_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
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BACKOFF_SETUP(%o2)
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ATOMIC_PRE_BARRIER
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1: lduw [%o1], %g1
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sub %g1, %o0, %g7
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cas [%o1], %g1, %g7
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cmp %g1, %g7
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bne,pn %icc, 2f
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sub %g7, %o0, %g7
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sra %g7, 0, %o0
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ATOMIC_POST_BARRIER
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retl
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nop
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2: BACKOFF_SPIN(%o2, %o3, 1b)
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.size atomic_sub_ret, .-atomic_sub_ret
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.globl atomic64_add
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.type atomic64_add,#function
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atomic64_add: /* %o0 = increment, %o1 = atomic_ptr */
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BACKOFF_SETUP(%o2)
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1: ldx [%o1], %g1
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add %g1, %o0, %g7
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casx [%o1], %g1, %g7
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cmp %g1, %g7
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bne,pn %xcc, 2f
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nop
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retl
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nop
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2: BACKOFF_SPIN(%o2, %o3, 1b)
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.size atomic64_add, .-atomic64_add
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.globl atomic64_sub
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.type atomic64_sub,#function
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atomic64_sub: /* %o0 = decrement, %o1 = atomic_ptr */
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BACKOFF_SETUP(%o2)
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1: ldx [%o1], %g1
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sub %g1, %o0, %g7
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casx [%o1], %g1, %g7
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cmp %g1, %g7
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bne,pn %xcc, 2f
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nop
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retl
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nop
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2: BACKOFF_SPIN(%o2, %o3, 1b)
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.size atomic64_sub, .-atomic64_sub
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.globl atomic64_add_ret
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.type atomic64_add_ret,#function
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atomic64_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
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BACKOFF_SETUP(%o2)
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ATOMIC_PRE_BARRIER
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1: ldx [%o1], %g1
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add %g1, %o0, %g7
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casx [%o1], %g1, %g7
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cmp %g1, %g7
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bne,pn %xcc, 2f
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add %g7, %o0, %g7
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mov %g7, %o0
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ATOMIC_POST_BARRIER
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retl
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nop
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2: BACKOFF_SPIN(%o2, %o3, 1b)
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.size atomic64_add_ret, .-atomic64_add_ret
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.globl atomic64_sub_ret
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.type atomic64_sub_ret,#function
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atomic64_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
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BACKOFF_SETUP(%o2)
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ATOMIC_PRE_BARRIER
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1: ldx [%o1], %g1
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sub %g1, %o0, %g7
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casx [%o1], %g1, %g7
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cmp %g1, %g7
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bne,pn %xcc, 2f
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sub %g7, %o0, %g7
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mov %g7, %o0
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ATOMIC_POST_BARRIER
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retl
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nop
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2: BACKOFF_SPIN(%o2, %o3, 1b)
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.size atomic64_sub_ret, .-atomic64_sub_ret
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