1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
121 lines
3.6 KiB
C
121 lines
3.6 KiB
C
/*
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* linux/include/asm-arm/arch-clps711x/syspld.h
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*
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* System Control PLD register definitions.
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*
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_SYSPLD_H
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#define __ASM_ARCH_SYSPLD_H
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#define SYSPLD_PHYS_BASE (0x10000000)
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#ifndef __ASSEMBLY__
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#include <asm/types.h>
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#define SYSPLD_REG(type,off) (*(volatile type *)(SYSPLD_BASE + off))
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#else
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#define SYSPLD_REG(type,off) (off)
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#endif
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#define PLD_INT SYSPLD_REG(u32, 0x000000)
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#define PLD_INT_PENIRQ (1 << 5)
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#define PLD_INT_UCB_IRQ (1 << 1)
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#define PLD_INT_KBD_ATN (1 << 0) /* EINT1 */
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#define PLD_PWR SYSPLD_REG(u32, 0x000004)
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#define PLD_PWR_EXT (1 << 5)
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#define PLD_PWR_MODE (1 << 4) /* 1 = PWM, 0 = PFM */
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#define PLD_S4_ON (1 << 3) /* LCD bias voltage enable */
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#define PLD_S3_ON (1 << 2) /* LCD backlight enable */
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#define PLD_S2_ON (1 << 1) /* LCD 3V3 supply enable */
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#define PLD_S1_ON (1 << 0) /* LCD 3V supply enable */
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#define PLD_KBD SYSPLD_REG(u32, 0x000008)
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#define PLD_KBD_WAKE (1 << 1)
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#define PLD_KBD_EN (1 << 0)
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#define PLD_SPI SYSPLD_REG(u32, 0x00000c)
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#define PLD_SPI_EN (1 << 0)
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#define PLD_IO SYSPLD_REG(u32, 0x000010)
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#define PLD_IO_BOOTSEL (1 << 6) /* boot sel switch */
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#define PLD_IO_USER (1 << 5) /* user defined switch */
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#define PLD_IO_LED3 (1 << 4)
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#define PLD_IO_LED2 (1 << 3)
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#define PLD_IO_LED1 (1 << 2)
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#define PLD_IO_LED0 (1 << 1)
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#define PLD_IO_LEDEN (1 << 0)
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#define PLD_IRDA SYSPLD_REG(u32, 0x000014)
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#define PLD_IRDA_EN (1 << 0)
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#define PLD_COM2 SYSPLD_REG(u32, 0x000018)
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#define PLD_COM2_EN (1 << 0)
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#define PLD_COM1 SYSPLD_REG(u32, 0x00001c)
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#define PLD_COM1_EN (1 << 0)
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#define PLD_AUD SYSPLD_REG(u32, 0x000020)
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#define PLD_AUD_DIV1 (1 << 6)
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#define PLD_AUD_DIV0 (1 << 5)
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#define PLD_AUD_CLK_SEL1 (1 << 4)
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#define PLD_AUD_CLK_SEL0 (1 << 3)
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#define PLD_AUD_MIC_PWR (1 << 2)
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#define PLD_AUD_MIC_GAIN (1 << 1)
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#define PLD_AUD_CODEC_EN (1 << 0)
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#define PLD_CF SYSPLD_REG(u32, 0x000024)
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#define PLD_CF2_SLEEP (1 << 5)
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#define PLD_CF1_SLEEP (1 << 4)
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#define PLD_CF2_nPDREQ (1 << 3)
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#define PLD_CF1_nPDREQ (1 << 2)
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#define PLD_CF2_nIRQ (1 << 1)
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#define PLD_CF1_nIRQ (1 << 0)
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#define PLD_SDC SYSPLD_REG(u32, 0x000028)
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#define PLD_SDC_INT_EN (1 << 2)
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#define PLD_SDC_WP (1 << 1)
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#define PLD_SDC_CD (1 << 0)
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#define PLD_FPGA SYSPLD_REG(u32, 0x00002c)
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#define PLD_CODEC SYSPLD_REG(u32, 0x400000)
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#define PLD_CODEC_IRQ3 (1 << 4)
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#define PLD_CODEC_IRQ2 (1 << 3)
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#define PLD_CODEC_IRQ1 (1 << 2)
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#define PLD_CODEC_EN (1 << 0)
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#define PLD_BRITE SYSPLD_REG(u32, 0x400004)
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#define PLD_BRITE_UP (1 << 1)
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#define PLD_BRITE_DN (1 << 0)
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#define PLD_LCDEN SYSPLD_REG(u32, 0x400008)
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#define PLD_LCDEN_EN (1 << 0)
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#define PLD_ID SYSPLD_REG(u32, 0x40000c)
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#define PLD_TCH SYSPLD_REG(u32, 0x400010)
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#define PLD_TCH_PENIRQ (1 << 1)
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#define PLD_TCH_EN (1 << 0)
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#define PLD_GPIO SYSPLD_REG(u32, 0x400014)
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#define PLD_GPIO2 (1 << 2)
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#define PLD_GPIO1 (1 << 1)
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#define PLD_GPIO0 (1 << 0)
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#endif
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