499ccb27a8
Standarize and document the FPGA nodes used on Freescale QorIQ reference boards. There are different kinds of FPGAs used on the boards, but only two are currently standard: "pixis", "ngpixis", and "qixis". Although there are minor differences among the boards that have one kind of FPGA, most of the functionality is the same, so it makes sense to create common compatibility strings. We also need to update the P1022DS platform file, because the compatible string for its PIXIS node has changed. This means that older kernels are not compatible with newer device trees. This is not a real problem, however, since that particular function doesn't work anyway. When the DIU is active, the PIXIS is in "indirect mode", and so cannot be accessed as a memory-mapped device. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
172 lines
4.5 KiB
Text
172 lines
4.5 KiB
Text
/*
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* P4080DS Device Tree Source
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*
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* Copyright 2009-2011 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/include/ "p4080si.dtsi"
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/ {
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model = "fsl,P4080DS";
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compatible = "fsl,P4080DS";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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memory {
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device_type = "memory";
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};
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soc: soc@ffe000000 {
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spi@110000 {
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spansion,s25sl12801";
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reg = <0>;
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spi-max-frequency = <40000000>; /* input clock */
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partition@u-boot {
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label = "u-boot";
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reg = <0x00000000 0x00100000>;
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read-only;
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};
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partition@kernel {
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label = "kernel";
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reg = <0x00100000 0x00500000>;
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read-only;
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};
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partition@dtb {
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label = "dtb";
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reg = <0x00600000 0x00100000>;
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read-only;
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};
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partition@fs {
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label = "file system";
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reg = <0x00700000 0x00900000>;
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};
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};
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};
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i2c@118100 {
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eeprom@51 {
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compatible = "at24,24c256";
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reg = <0x51>;
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};
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eeprom@52 {
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compatible = "at24,24c256";
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reg = <0x52>;
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};
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rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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interrupts = <0x1 0x1 0 0>;
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};
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};
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usb0: usb@210000 {
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phy_type = "ulpi";
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};
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usb1: usb@211000 {
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dr_mode = "host";
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phy_type = "ulpi";
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};
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};
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rapidio0: rapidio@ffe0c0000 {
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reg = <0xf 0xfe0c0000 0 0x20000>;
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ranges = <0 0 0xc 0x20000000 0 0x01000000>;
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};
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localbus@ffe124000 {
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reg = <0xf 0xfe124000 0 0x1000>;
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ranges = <0 0 0xf 0xe8000000 0x08000000
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3 0 0xf 0xffdf0000 0x00008000>;
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flash@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x08000000>;
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bank-width = <2>;
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device-width = <2>;
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};
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board-control@3,0 {
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compatible = "fsl,p4080ds-fpga", "fsl,fpga-ngpixis";
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reg = <3 0 0x30>;
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};
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};
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pci0: pcie@ffe200000 {
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reg = <0xf 0xfe200000 0 0x1000>;
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ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
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0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x20000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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pci1: pcie@ffe201000 {
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reg = <0xf 0xfe201000 0 0x1000>;
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ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
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0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x20000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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pci2: pcie@ffe202000 {
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reg = <0xf 0xfe202000 0 0x1000>;
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ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
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0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x20000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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};
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