3a1e501511
Patch from George G. Davis As noted in http://www.arm.com/linux/patch-2.6.9-arm1.gz, the "Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR." So the v6_early_abort handler does not report the correct rd/wr direction for the SWP instruction which may result in SEGVS or hangs. In order to work around this problem, this patch merely updates the fix contained in the ARM Ltd. patch to use the macroised abort handler fixups. Signed-off-by: George G. Davis Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
39 lines
1.1 KiB
ArmAsm
39 lines
1.1 KiB
ArmAsm
#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include "abort-macro.S"
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/*
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* Function: v6_early_abort
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*
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* Params : r2 = address of aborted instruction
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* : r3 = saved SPSR
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*
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* Returns : r0 = address of abort
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* : r1 = FSR, bit 11 = write
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* : r2-r8 = corrupted
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* : r9 = preserved
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* : sp = pointer to registers
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*
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* Purpose : obtain information about current aborted instruction.
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* Note: we read user space. This means we might cause a data
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* abort here if the I-TLB and D-TLB aren't seeing the same
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* picture. Unfortunately, this does happen. We live with it.
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*/
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.align 5
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ENTRY(v6_early_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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/*
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* Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.
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* The test below covers all the write situations, including Java bytecodes
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*/
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bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
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tst r3, #PSR_J_BIT @ Java?
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movne pc, lr
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do_thumb_abort
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ldreq r3, [r2] @ read aborted ARM instruction
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do_ldrd_abort
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tst r3, #1 << 20 @ L = 0 -> write
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orreq r1, r1, #1 << 11 @ yes.
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mov pc, lr
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