faa7bc51c1
ARMv7 SMP hardware can handle the TLB maintenance operations broadcasting in hardware so that the software can avoid the costly IPIs. This patch adds the necessary checks (the MMFR3 CPUID register) to avoid the broadcasting if already supported by the hardware. (this patch is based on the work done by Tony Thompson @ ARM) Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
96 lines
2.4 KiB
ArmAsm
96 lines
2.4 KiB
ArmAsm
/*
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* linux/arch/arm/mm/tlb-v7.S
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*
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* Copyright (C) 1997-2002 Russell King
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* Modified for ARMv7 by Catalin Marinas
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* ARM architecture version 6 TLB handling functions.
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* These assume a split I/D TLB.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/page.h>
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#include <asm/tlbflush.h>
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#include "proc-macros.S"
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/*
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* v7wbi_flush_user_tlb_range(start, end, vma)
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*
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* Invalidate a range of TLB entries in the specified address space.
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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* - vma - vma_struct describing address range
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*
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* It is assumed that:
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* - the "Invalidate single entry" instruction will invalidate
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* both the I and the D TLBs on Harvard-style TLBs
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*/
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ENTRY(v7wbi_flush_user_tlb_range)
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vma_vm_mm r3, r2 @ get vma->vm_mm
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mmid r3, r3 @ get vm_mm->context.id
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dsb
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mov r0, r0, lsr #PAGE_SHIFT @ align address
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mov r1, r1, lsr #PAGE_SHIFT
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asid r3, r3 @ mask ASID
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orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
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mov r1, r1, lsl #PAGE_SHIFT
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vma_vm_flags r2, r2 @ get vma->vm_flags
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1:
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#ifdef CONFIG_SMP
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mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable)
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#else
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mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA
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#endif
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add r0, r0, #PAGE_SZ
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cmp r0, r1
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blo 1b
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mov ip, #0
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mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB
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dsb
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mov pc, lr
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ENDPROC(v7wbi_flush_user_tlb_range)
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/*
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* v7wbi_flush_kern_tlb_range(start,end)
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*
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* Invalidate a range of kernel TLB entries
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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*/
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ENTRY(v7wbi_flush_kern_tlb_range)
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dsb
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mov r0, r0, lsr #PAGE_SHIFT @ align address
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mov r1, r1, lsr #PAGE_SHIFT
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mov r0, r0, lsl #PAGE_SHIFT
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mov r1, r1, lsl #PAGE_SHIFT
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1:
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#ifdef CONFIG_SMP
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mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable)
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#else
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mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA
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#endif
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add r0, r0, #PAGE_SZ
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cmp r0, r1
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blo 1b
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mov r2, #0
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mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
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dsb
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isb
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mov pc, lr
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ENDPROC(v7wbi_flush_kern_tlb_range)
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__INIT
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.type v7wbi_tlb_fns, #object
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ENTRY(v7wbi_tlb_fns)
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.long v7wbi_flush_user_tlb_range
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.long v7wbi_flush_kern_tlb_range
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.long v7wbi_tlb_flags
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.size v7wbi_tlb_fns, . - v7wbi_tlb_fns
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