dca3edb88e
mac80211 has RX A-MPDU reordering support. Use that and remove redundant RX processing within the driver. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
754 lines
20 KiB
C
754 lines
20 KiB
C
/*
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* Copyright (c) 2008 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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* Implementation of receive path.
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*/
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#include "core.h"
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/*
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* Setup and link descriptors.
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*
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* 11N: we can no longer afford to self link the last descriptor.
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* MAC acknowledges BA status as long as it copies frames to host
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* buffer (or rx fifo). This can incorrectly acknowledge packets
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* to a sender if last desc is self-linked.
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*
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* NOTE: Caller should hold the rxbuf lock.
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*/
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static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
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{
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struct ath_hal *ah = sc->sc_ah;
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struct ath_desc *ds;
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struct sk_buff *skb;
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ATH_RXBUF_RESET(bf);
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ds = bf->bf_desc;
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ds->ds_link = 0; /* link to null */
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ds->ds_data = bf->bf_buf_addr;
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/* XXX For RADAR?
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* virtual addr of the beginning of the buffer. */
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skb = bf->bf_mpdu;
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ASSERT(skb != NULL);
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ds->ds_vdata = skb->data;
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/* setup rx descriptors */
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ath9k_hw_setuprxdesc(ah,
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ds,
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skb_tailroom(skb), /* buffer size */
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0);
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if (sc->sc_rxlink == NULL)
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ath9k_hw_putrxbuf(ah, bf->bf_daddr);
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else
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*sc->sc_rxlink = bf->bf_daddr;
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sc->sc_rxlink = &ds->ds_link;
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ath9k_hw_rxena(ah);
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}
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static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc,
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u32 len)
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{
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struct sk_buff *skb;
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u32 off;
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/*
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* Cache-line-align. This is important (for the
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* 5210 at least) as not doing so causes bogus data
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* in rx'd frames.
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*/
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skb = dev_alloc_skb(len + sc->sc_cachelsz - 1);
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if (skb != NULL) {
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off = ((unsigned long) skb->data) % sc->sc_cachelsz;
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if (off != 0)
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skb_reserve(skb, sc->sc_cachelsz - off);
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} else {
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DPRINTF(sc, ATH_DBG_FATAL,
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"%s: skbuff alloc of size %u failed\n",
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__func__, len);
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return NULL;
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}
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return skb;
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}
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static void ath_rx_requeue(struct ath_softc *sc, struct sk_buff *skb)
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{
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struct ath_buf *bf = ATH_RX_CONTEXT(skb)->ctx_rxbuf;
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ASSERT(bf != NULL);
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spin_lock_bh(&sc->sc_rxbuflock);
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if (bf->bf_status & ATH_BUFSTATUS_STALE) {
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/*
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* This buffer is still held for hw acess.
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* Mark it as free to be re-queued it later.
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*/
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bf->bf_status |= ATH_BUFSTATUS_FREE;
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} else {
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/* XXX: we probably never enter here, remove after
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* verification */
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list_add_tail(&bf->list, &sc->sc_rxbuf);
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ath_rx_buf_link(sc, bf);
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}
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spin_unlock_bh(&sc->sc_rxbuflock);
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}
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/*
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* The skb indicated to upper stack won't be returned to us.
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* So we have to allocate a new one and queue it by ourselves.
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*/
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static int ath_rx_indicate(struct ath_softc *sc,
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struct sk_buff *skb,
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struct ath_recv_status *status,
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u16 keyix)
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{
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struct ath_buf *bf = ATH_RX_CONTEXT(skb)->ctx_rxbuf;
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struct sk_buff *nskb;
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int type;
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/* indicate frame to the stack, which will free the old skb. */
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type = _ath_rx_indicate(sc, skb, status, keyix);
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/* allocate a new skb and queue it to for H/W processing */
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nskb = ath_rxbuf_alloc(sc, sc->sc_rxbufsize);
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if (nskb != NULL) {
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bf->bf_mpdu = nskb;
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bf->bf_buf_addr = pci_map_single(sc->pdev, nskb->data,
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skb_end_pointer(nskb) - nskb->head,
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PCI_DMA_FROMDEVICE);
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bf->bf_dmacontext = bf->bf_buf_addr;
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ATH_RX_CONTEXT(nskb)->ctx_rxbuf = bf;
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/* queue the new wbuf to H/W */
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ath_rx_requeue(sc, nskb);
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}
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return type;
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}
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static void ath_opmode_init(struct ath_softc *sc)
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{
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struct ath_hal *ah = sc->sc_ah;
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u32 rfilt, mfilt[2];
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/* configure rx filter */
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rfilt = ath_calcrxfilter(sc);
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ath9k_hw_setrxfilter(ah, rfilt);
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/* configure bssid mask */
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if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
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ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
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/* configure operational mode */
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ath9k_hw_setopmode(ah);
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/* Handle any link-level address change. */
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ath9k_hw_setmac(ah, sc->sc_myaddr);
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/* calculate and install multicast filter */
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mfilt[0] = mfilt[1] = ~0;
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ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
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DPRINTF(sc, ATH_DBG_CONFIG ,
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"%s: RX filter 0x%x, MC filter %08x:%08x\n",
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__func__, rfilt, mfilt[0], mfilt[1]);
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}
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int ath_rx_init(struct ath_softc *sc, int nbufs)
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{
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struct sk_buff *skb;
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struct ath_buf *bf;
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int error = 0;
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do {
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spin_lock_init(&sc->sc_rxflushlock);
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sc->sc_flags &= ~SC_OP_RXFLUSH;
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spin_lock_init(&sc->sc_rxbuflock);
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/*
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* Cisco's VPN software requires that drivers be able to
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* receive encapsulated frames that are larger than the MTU.
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* Since we can't be sure how large a frame we'll get, setup
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* to handle the larges on possible.
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*/
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sc->sc_rxbufsize = roundup(IEEE80211_MAX_MPDU_LEN,
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min(sc->sc_cachelsz,
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(u16)64));
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DPRINTF(sc, ATH_DBG_CONFIG, "%s: cachelsz %u rxbufsize %u\n",
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__func__, sc->sc_cachelsz, sc->sc_rxbufsize);
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/* Initialize rx descriptors */
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error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
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"rx", nbufs, 1);
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if (error != 0) {
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DPRINTF(sc, ATH_DBG_FATAL,
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"%s: failed to allocate rx descriptors: %d\n",
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__func__, error);
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break;
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}
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/* Pre-allocate a wbuf for each rx buffer */
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list_for_each_entry(bf, &sc->sc_rxbuf, list) {
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skb = ath_rxbuf_alloc(sc, sc->sc_rxbufsize);
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if (skb == NULL) {
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error = -ENOMEM;
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break;
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}
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bf->bf_mpdu = skb;
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bf->bf_buf_addr = pci_map_single(sc->pdev, skb->data,
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skb_end_pointer(skb) - skb->head,
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PCI_DMA_FROMDEVICE);
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bf->bf_dmacontext = bf->bf_buf_addr;
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ATH_RX_CONTEXT(skb)->ctx_rxbuf = bf;
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}
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sc->sc_rxlink = NULL;
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} while (0);
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if (error)
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ath_rx_cleanup(sc);
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return error;
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}
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/* Reclaim all rx queue resources */
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void ath_rx_cleanup(struct ath_softc *sc)
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{
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struct sk_buff *skb;
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struct ath_buf *bf;
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list_for_each_entry(bf, &sc->sc_rxbuf, list) {
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skb = bf->bf_mpdu;
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if (skb)
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dev_kfree_skb(skb);
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}
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/* cleanup rx descriptors */
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if (sc->sc_rxdma.dd_desc_len != 0)
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ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
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}
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/*
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* Calculate the receive filter according to the
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* operating mode and state:
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*
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* o always accept unicast, broadcast, and multicast traffic
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* o maintain current state of phy error reception (the hal
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* may enable phy error frames for noise immunity work)
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* o probe request frames are accepted only when operating in
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* hostap, adhoc, or monitor modes
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* o enable promiscuous mode according to the interface state
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* o accept beacons:
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* - when operating in adhoc mode so the 802.11 layer creates
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* node table entries for peers,
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* - when operating in station mode for collecting rssi data when
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* the station is otherwise quiet, or
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* - when operating as a repeater so we see repeater-sta beacons
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* - when scanning
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*/
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u32 ath_calcrxfilter(struct ath_softc *sc)
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{
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#define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
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u32 rfilt;
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rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
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| ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
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| ATH9K_RX_FILTER_MCAST;
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/* If not a STA, enable processing of Probe Requests */
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if (sc->sc_ah->ah_opmode != ATH9K_M_STA)
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rfilt |= ATH9K_RX_FILTER_PROBEREQ;
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/* Can't set HOSTAP into promiscous mode */
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if (((sc->sc_ah->ah_opmode != ATH9K_M_HOSTAP) &&
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(sc->rx_filter & FIF_PROMISC_IN_BSS)) ||
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(sc->sc_ah->ah_opmode == ATH9K_M_MONITOR)) {
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rfilt |= ATH9K_RX_FILTER_PROM;
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/* ??? To prevent from sending ACK */
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rfilt &= ~ATH9K_RX_FILTER_UCAST;
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}
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if (((sc->sc_ah->ah_opmode == ATH9K_M_STA) &&
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(sc->rx_filter & FIF_BCN_PRBRESP_PROMISC)) ||
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(sc->sc_ah->ah_opmode == ATH9K_M_IBSS))
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rfilt |= ATH9K_RX_FILTER_BEACON;
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/* If in HOSTAP mode, want to enable reception of PSPOLL frames
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& beacon frames */
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if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP)
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rfilt |= (ATH9K_RX_FILTER_BEACON | ATH9K_RX_FILTER_PSPOLL);
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return rfilt;
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#undef RX_FILTER_PRESERVE
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}
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/* Enable the receive h/w following a reset. */
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int ath_startrecv(struct ath_softc *sc)
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{
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struct ath_hal *ah = sc->sc_ah;
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struct ath_buf *bf, *tbf;
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spin_lock_bh(&sc->sc_rxbuflock);
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if (list_empty(&sc->sc_rxbuf))
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goto start_recv;
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sc->sc_rxlink = NULL;
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list_for_each_entry_safe(bf, tbf, &sc->sc_rxbuf, list) {
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if (bf->bf_status & ATH_BUFSTATUS_STALE) {
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/* restarting h/w, no need for holding descriptors */
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bf->bf_status &= ~ATH_BUFSTATUS_STALE;
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/*
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* Upper layer may not be done with the frame yet so
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* we can't just re-queue it to hardware. Remove it
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* from h/w queue. It'll be re-queued when upper layer
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* returns the frame and ath_rx_requeue_mpdu is called.
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*/
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if (!(bf->bf_status & ATH_BUFSTATUS_FREE)) {
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list_del(&bf->list);
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continue;
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}
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}
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/* chain descriptors */
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ath_rx_buf_link(sc, bf);
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}
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/* We could have deleted elements so the list may be empty now */
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if (list_empty(&sc->sc_rxbuf))
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goto start_recv;
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bf = list_first_entry(&sc->sc_rxbuf, struct ath_buf, list);
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ath9k_hw_putrxbuf(ah, bf->bf_daddr);
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ath9k_hw_rxena(ah); /* enable recv descriptors */
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start_recv:
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spin_unlock_bh(&sc->sc_rxbuflock);
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ath_opmode_init(sc); /* set filters, etc. */
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ath9k_hw_startpcureceive(ah); /* re-enable PCU/DMA engine */
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return 0;
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}
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/* Disable the receive h/w in preparation for a reset. */
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bool ath_stoprecv(struct ath_softc *sc)
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{
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struct ath_hal *ah = sc->sc_ah;
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u64 tsf;
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bool stopped;
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ath9k_hw_stoppcurecv(ah); /* disable PCU */
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ath9k_hw_setrxfilter(ah, 0); /* clear recv filter */
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stopped = ath9k_hw_stopdmarecv(ah); /* disable DMA engine */
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mdelay(3); /* 3ms is long enough for 1 frame */
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tsf = ath9k_hw_gettsf64(ah);
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sc->sc_rxlink = NULL; /* just in case */
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return stopped;
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}
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/* Flush receive queue */
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void ath_flushrecv(struct ath_softc *sc)
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{
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/*
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* ath_rx_tasklet may be used to handle rx interrupt and flush receive
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* queue at the same time. Use a lock to serialize the access of rx
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* queue.
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* ath_rx_tasklet cannot hold the spinlock while indicating packets.
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* Instead, do not claim the spinlock but check for a flush in
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* progress (see references to sc_rxflush)
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*/
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spin_lock_bh(&sc->sc_rxflushlock);
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sc->sc_flags |= SC_OP_RXFLUSH;
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ath_rx_tasklet(sc, 1);
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sc->sc_flags &= ~SC_OP_RXFLUSH;
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spin_unlock_bh(&sc->sc_rxflushlock);
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}
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/* Process receive queue, as well as LED, etc. */
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int ath_rx_tasklet(struct ath_softc *sc, int flush)
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{
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#define PA2DESC(_sc, _pa) \
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((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
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((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
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struct ath_buf *bf, *bf_held = NULL;
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struct ath_desc *ds;
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struct ieee80211_hdr *hdr;
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struct sk_buff *skb = NULL;
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struct ath_recv_status rx_status;
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struct ath_hal *ah = sc->sc_ah;
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int type, rx_processed = 0;
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u32 phyerr;
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u8 chainreset = 0;
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int retval;
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__le16 fc;
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do {
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/* If handling rx interrupt and flush is in progress => exit */
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if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
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break;
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spin_lock_bh(&sc->sc_rxbuflock);
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if (list_empty(&sc->sc_rxbuf)) {
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sc->sc_rxlink = NULL;
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spin_unlock_bh(&sc->sc_rxbuflock);
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break;
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}
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bf = list_first_entry(&sc->sc_rxbuf, struct ath_buf, list);
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/*
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* There is a race condition that BH gets scheduled after sw
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* writes RxE and before hw re-load the last descriptor to get
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* the newly chained one. Software must keep the last DONE
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* descriptor as a holding descriptor - software does so by
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* marking it with the STALE flag.
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*/
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if (bf->bf_status & ATH_BUFSTATUS_STALE) {
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bf_held = bf;
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if (list_is_last(&bf_held->list, &sc->sc_rxbuf)) {
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/*
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* The holding descriptor is the last
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* descriptor in queue. It's safe to
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* remove the last holding descriptor
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* in BH context.
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*/
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list_del(&bf_held->list);
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bf_held->bf_status &= ~ATH_BUFSTATUS_STALE;
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sc->sc_rxlink = NULL;
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if (bf_held->bf_status & ATH_BUFSTATUS_FREE) {
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list_add_tail(&bf_held->list,
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&sc->sc_rxbuf);
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ath_rx_buf_link(sc, bf_held);
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}
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spin_unlock_bh(&sc->sc_rxbuflock);
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break;
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}
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bf = list_entry(bf->list.next, struct ath_buf, list);
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}
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ds = bf->bf_desc;
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++rx_processed;
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/*
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* Must provide the virtual address of the current
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* descriptor, the physical address, and the virtual
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* address of the next descriptor in the h/w chain.
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* This allows the HAL to look ahead to see if the
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* hardware is done with a descriptor by checking the
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* done bit in the following descriptor and the address
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* of the current descriptor the DMA engine is working
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* on. All this is necessary because of our use of
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* a self-linked list to avoid rx overruns.
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*/
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retval = ath9k_hw_rxprocdesc(ah,
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ds,
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bf->bf_daddr,
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PA2DESC(sc, ds->ds_link),
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0);
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if (retval == -EINPROGRESS) {
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struct ath_buf *tbf;
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struct ath_desc *tds;
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if (list_is_last(&bf->list, &sc->sc_rxbuf)) {
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spin_unlock_bh(&sc->sc_rxbuflock);
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break;
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}
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tbf = list_entry(bf->list.next, struct ath_buf, list);
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/*
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|
* On some hardware the descriptor status words could
|
|
* get corrupted, including the done bit. Because of
|
|
* this, check if the next descriptor's done bit is
|
|
* set or not.
|
|
*
|
|
* If the next descriptor's done bit is set, the current
|
|
* descriptor has been corrupted. Force s/w to discard
|
|
* this descriptor and continue...
|
|
*/
|
|
|
|
tds = tbf->bf_desc;
|
|
retval = ath9k_hw_rxprocdesc(ah,
|
|
tds, tbf->bf_daddr,
|
|
PA2DESC(sc, tds->ds_link), 0);
|
|
if (retval == -EINPROGRESS) {
|
|
spin_unlock_bh(&sc->sc_rxbuflock);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* XXX: we do not support frames spanning
|
|
* multiple descriptors */
|
|
bf->bf_status |= ATH_BUFSTATUS_DONE;
|
|
|
|
skb = bf->bf_mpdu;
|
|
if (skb == NULL) { /* XXX ??? can this happen */
|
|
spin_unlock_bh(&sc->sc_rxbuflock);
|
|
continue;
|
|
}
|
|
/*
|
|
* Now we know it's a completed frame, we can indicate the
|
|
* frame. Remove the previous holding descriptor and leave
|
|
* this one in the queue as the new holding descriptor.
|
|
*/
|
|
if (bf_held) {
|
|
list_del(&bf_held->list);
|
|
bf_held->bf_status &= ~ATH_BUFSTATUS_STALE;
|
|
if (bf_held->bf_status & ATH_BUFSTATUS_FREE) {
|
|
list_add_tail(&bf_held->list, &sc->sc_rxbuf);
|
|
/* try to requeue this descriptor */
|
|
ath_rx_buf_link(sc, bf_held);
|
|
}
|
|
}
|
|
|
|
bf->bf_status |= ATH_BUFSTATUS_STALE;
|
|
bf_held = bf;
|
|
/*
|
|
* Release the lock here in case ieee80211_input() return
|
|
* the frame immediately by calling ath_rx_mpdu_requeue().
|
|
*/
|
|
spin_unlock_bh(&sc->sc_rxbuflock);
|
|
|
|
if (flush) {
|
|
/*
|
|
* If we're asked to flush receive queue, directly
|
|
* chain it back at the queue without processing it.
|
|
*/
|
|
goto rx_next;
|
|
}
|
|
|
|
hdr = (struct ieee80211_hdr *)skb->data;
|
|
fc = hdr->frame_control;
|
|
memset(&rx_status, 0, sizeof(struct ath_recv_status));
|
|
|
|
if (ds->ds_rxstat.rs_more) {
|
|
/*
|
|
* Frame spans multiple descriptors; this
|
|
* cannot happen yet as we don't support
|
|
* jumbograms. If not in monitor mode,
|
|
* discard the frame.
|
|
*/
|
|
#ifndef ERROR_FRAMES
|
|
/*
|
|
* Enable this if you want to see
|
|
* error frames in Monitor mode.
|
|
*/
|
|
if (sc->sc_ah->ah_opmode != ATH9K_M_MONITOR)
|
|
goto rx_next;
|
|
#endif
|
|
/* fall thru for monitor mode handling... */
|
|
} else if (ds->ds_rxstat.rs_status != 0) {
|
|
if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC)
|
|
rx_status.flags |= ATH_RX_FCS_ERROR;
|
|
if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY) {
|
|
phyerr = ds->ds_rxstat.rs_phyerr & 0x1f;
|
|
goto rx_next;
|
|
}
|
|
|
|
if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT) {
|
|
/*
|
|
* Decrypt error. We only mark packet status
|
|
* here and always push up the frame up to let
|
|
* mac80211 handle the actual error case, be
|
|
* it no decryption key or real decryption
|
|
* error. This let us keep statistics there.
|
|
*/
|
|
rx_status.flags |= ATH_RX_DECRYPT_ERROR;
|
|
} else if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC) {
|
|
/*
|
|
* Demic error. We only mark frame status here
|
|
* and always push up the frame up to let
|
|
* mac80211 handle the actual error case. This
|
|
* let us keep statistics there. Hardware may
|
|
* post a false-positive MIC error.
|
|
*/
|
|
if (ieee80211_is_ctl(fc))
|
|
/*
|
|
* Sometimes, we get invalid
|
|
* MIC failures on valid control frames.
|
|
* Remove these mic errors.
|
|
*/
|
|
ds->ds_rxstat.rs_status &=
|
|
~ATH9K_RXERR_MIC;
|
|
else
|
|
rx_status.flags |= ATH_RX_MIC_ERROR;
|
|
}
|
|
/*
|
|
* Reject error frames with the exception of
|
|
* decryption and MIC failures. For monitor mode,
|
|
* we also ignore the CRC error.
|
|
*/
|
|
if (sc->sc_ah->ah_opmode == ATH9K_M_MONITOR) {
|
|
if (ds->ds_rxstat.rs_status &
|
|
~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
|
|
ATH9K_RXERR_CRC))
|
|
goto rx_next;
|
|
} else {
|
|
if (ds->ds_rxstat.rs_status &
|
|
~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
|
|
goto rx_next;
|
|
}
|
|
}
|
|
}
|
|
/*
|
|
* The status portion of the descriptor could get corrupted.
|
|
*/
|
|
if (sc->sc_rxbufsize < ds->ds_rxstat.rs_datalen)
|
|
goto rx_next;
|
|
/*
|
|
* Sync and unmap the frame. At this point we're
|
|
* committed to passing the sk_buff somewhere so
|
|
* clear buf_skb; this means a new sk_buff must be
|
|
* allocated when the rx descriptor is setup again
|
|
* to receive another frame.
|
|
*/
|
|
skb_put(skb, ds->ds_rxstat.rs_datalen);
|
|
skb->protocol = cpu_to_be16(ETH_P_CONTROL);
|
|
rx_status.tsf = ath_extend_tsf(sc, ds->ds_rxstat.rs_tstamp);
|
|
rx_status.rateieee =
|
|
sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate;
|
|
rx_status.rateKbps =
|
|
sc->sc_hwmap[ds->ds_rxstat.rs_rate].rateKbps;
|
|
rx_status.ratecode = ds->ds_rxstat.rs_rate;
|
|
|
|
/* HT rate */
|
|
if (rx_status.ratecode & 0x80) {
|
|
/* TODO - add table to avoid division */
|
|
if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) {
|
|
rx_status.flags |= ATH_RX_40MHZ;
|
|
rx_status.rateKbps =
|
|
(rx_status.rateKbps * 27) / 13;
|
|
}
|
|
if (ds->ds_rxstat.rs_flags & ATH9K_RX_GI)
|
|
rx_status.rateKbps =
|
|
(rx_status.rateKbps * 10) / 9;
|
|
else
|
|
rx_status.flags |= ATH_RX_SHORT_GI;
|
|
}
|
|
|
|
/* sc_noise_floor is only available when the station
|
|
attaches to an AP, so we use a default value
|
|
if we are not yet attached. */
|
|
rx_status.abs_rssi =
|
|
ds->ds_rxstat.rs_rssi + sc->sc_ani.sc_noise_floor;
|
|
|
|
pci_dma_sync_single_for_cpu(sc->pdev,
|
|
bf->bf_buf_addr,
|
|
skb_tailroom(skb),
|
|
PCI_DMA_FROMDEVICE);
|
|
pci_unmap_single(sc->pdev,
|
|
bf->bf_buf_addr,
|
|
sc->sc_rxbufsize,
|
|
PCI_DMA_FROMDEVICE);
|
|
|
|
/* XXX: Ah! make me more readable, use a helper */
|
|
if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
|
|
if (ds->ds_rxstat.rs_moreaggr == 0) {
|
|
rx_status.rssictl[0] =
|
|
ds->ds_rxstat.rs_rssi_ctl0;
|
|
rx_status.rssictl[1] =
|
|
ds->ds_rxstat.rs_rssi_ctl1;
|
|
rx_status.rssictl[2] =
|
|
ds->ds_rxstat.rs_rssi_ctl2;
|
|
rx_status.rssi = ds->ds_rxstat.rs_rssi;
|
|
if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) {
|
|
rx_status.rssiextn[0] =
|
|
ds->ds_rxstat.rs_rssi_ext0;
|
|
rx_status.rssiextn[1] =
|
|
ds->ds_rxstat.rs_rssi_ext1;
|
|
rx_status.rssiextn[2] =
|
|
ds->ds_rxstat.rs_rssi_ext2;
|
|
rx_status.flags |=
|
|
ATH_RX_RSSI_EXTN_VALID;
|
|
}
|
|
rx_status.flags |= ATH_RX_RSSI_VALID |
|
|
ATH_RX_CHAIN_RSSI_VALID;
|
|
}
|
|
} else {
|
|
/*
|
|
* Need to insert the "combined" rssi into the
|
|
* status structure for upper layer processing
|
|
*/
|
|
rx_status.rssi = ds->ds_rxstat.rs_rssi;
|
|
rx_status.flags |= ATH_RX_RSSI_VALID;
|
|
}
|
|
|
|
/* Pass frames up to the stack. */
|
|
|
|
type = ath_rx_indicate(sc, skb,
|
|
&rx_status, ds->ds_rxstat.rs_keyix);
|
|
|
|
/*
|
|
* change the default rx antenna if rx diversity chooses the
|
|
* other antenna 3 times in a row.
|
|
*/
|
|
if (sc->sc_defant != ds->ds_rxstat.rs_antenna) {
|
|
if (++sc->sc_rxotherant >= 3)
|
|
ath_setdefantenna(sc,
|
|
ds->ds_rxstat.rs_antenna);
|
|
} else {
|
|
sc->sc_rxotherant = 0;
|
|
}
|
|
|
|
#ifdef CONFIG_SLOW_ANT_DIV
|
|
if ((rx_status.flags & ATH_RX_RSSI_VALID) &&
|
|
ieee80211_is_beacon(fc)) {
|
|
ath_slow_ant_div(&sc->sc_antdiv, hdr, &ds->ds_rxstat);
|
|
}
|
|
#endif
|
|
/*
|
|
* For frames successfully indicated, the buffer will be
|
|
* returned to us by upper layers by calling
|
|
* ath_rx_mpdu_requeue, either synchronusly or asynchronously.
|
|
* So we don't want to do it here in this loop.
|
|
*/
|
|
continue;
|
|
|
|
rx_next:
|
|
bf->bf_status |= ATH_BUFSTATUS_FREE;
|
|
} while (TRUE);
|
|
|
|
if (chainreset) {
|
|
DPRINTF(sc, ATH_DBG_CONFIG,
|
|
"%s: Reset rx chain mask. "
|
|
"Do internal reset\n", __func__);
|
|
ASSERT(flush == 0);
|
|
ath_reset(sc, false);
|
|
}
|
|
|
|
return 0;
|
|
#undef PA2DESC
|
|
}
|