f264cc2824
Add PVR value and tests for 970MP. Also switch to a simpler (but slightly longer) check at init time for simplicity. Signed-off-by: Olof Johansson <olof@austin.ibm.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
234 lines
4.4 KiB
ArmAsm
234 lines
4.4 KiB
ArmAsm
/*
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* This file contains low level CPU setup functions.
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* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/config.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/ppc_asm.h>
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#include <asm/cputable.h>
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#include <asm/ppc_asm.h>
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#include <asm/offsets.h>
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#include <asm/cache.h>
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_GLOBAL(__970_cpu_preinit)
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/*
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* Do nothing if not running in HV mode
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*/
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mfmsr r0
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rldicl. r0,r0,4,63
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beqlr
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/*
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* Deal only with PPC970 and PPC970FX.
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*/
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mfspr r0,SPRN_PVR
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srwi r0,r0,16
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cmpwi r0,0x39
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beq 1f
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cmpwi r0,0x3c
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beq 1f
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cmpwi r0,0x44
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bnelr
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1:
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/* Make sure HID4:rm_ci is off before MMU is turned off, that large
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* pages are enabled with HID4:61 and clear HID5:DCBZ_size and
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* HID5:DCBZ32_ill
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*/
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li r0,0
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mfspr r3,SPRN_HID4
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rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
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rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
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sync
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mtspr SPRN_HID4,r3
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isync
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sync
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mfspr r3,SPRN_HID5
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rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
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sync
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mtspr SPRN_HID5,r3
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isync
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sync
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/* Setup some basic HID1 features */
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mfspr r0,SPRN_HID1
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li r3,0x1200 /* enable i-fetch cacheability */
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sldi r3,r3,44 /* and prefetch */
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or r0,r0,r3
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mtspr SPRN_HID1,r0
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mtspr SPRN_HID1,r0
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isync
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/* Clear HIOR */
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li r0,0
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sync
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mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
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isync
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blr
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_GLOBAL(__setup_cpu_power4)
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blr
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_GLOBAL(__setup_cpu_be)
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/* Set large page sizes LP=0: 16MB, LP=1: 64KB */
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addi r3, 0, 0
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ori r3, r3, HID6_LB
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sldi r3, r3, 32
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nor r3, r3, r3
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mfspr r4, SPRN_HID6
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and r4, r4, r3
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addi r3, 0, 0x02000
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sldi r3, r3, 32
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or r4, r4, r3
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mtspr SPRN_HID6, r4
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blr
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_GLOBAL(__setup_cpu_ppc970)
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mfspr r0,SPRN_HID0
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li r11,5 /* clear DOZE and SLEEP */
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rldimi r0,r11,52,8 /* set NAP and DPM */
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mtspr SPRN_HID0,r0
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mfspr r0,SPRN_HID0
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mfspr r0,SPRN_HID0
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mfspr r0,SPRN_HID0
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mfspr r0,SPRN_HID0
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mfspr r0,SPRN_HID0
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mfspr r0,SPRN_HID0
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sync
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isync
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blr
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/* Definitions for the table use to save CPU states */
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#define CS_HID0 0
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#define CS_HID1 8
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#define CS_HID4 16
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#define CS_HID5 24
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#define CS_SIZE 32
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.data
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.balign L1_CACHE_BYTES,0
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cpu_state_storage:
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.space CS_SIZE
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.balign L1_CACHE_BYTES,0
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.text
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/* Called in normal context to backup CPU 0 state. This
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* does not include cache settings. This function is also
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* called for machine sleep. This does not include the MMU
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* setup, BATs, etc... but rather the "special" registers
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* like HID0, HID1, HID4, etc...
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*/
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_GLOBAL(__save_cpu_setup)
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/* Some CR fields are volatile, we back it up all */
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mfcr r7
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/* Get storage ptr */
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LOADADDR(r5,cpu_state_storage)
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/* We only deal with 970 for now */
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mfspr r0,SPRN_PVR
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srwi r0,r0,16
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cmpwi r0,0x39
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beq 1f
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cmpwi r0,0x3c
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beq 1f
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cmpwi r0,0x44
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bne 2f
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1: /* Save HID0,1,4 and 5 */
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mfspr r3,SPRN_HID0
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std r3,CS_HID0(r5)
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mfspr r3,SPRN_HID1
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std r3,CS_HID1(r5)
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mfspr r3,SPRN_HID4
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std r3,CS_HID4(r5)
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mfspr r3,SPRN_HID5
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std r3,CS_HID5(r5)
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2:
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mtcr r7
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blr
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/* Called with no MMU context (typically MSR:IR/DR off) to
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* restore CPU state as backed up by the previous
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* function. This does not include cache setting
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*/
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_GLOBAL(__restore_cpu_setup)
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/* Get storage ptr (FIXME when using anton reloc as we
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* are running with translation disabled here
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*/
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LOADADDR(r5,cpu_state_storage)
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/* We only deal with 970 for now */
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mfspr r0,SPRN_PVR
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srwi r0,r0,16
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cmpwi r0,0x39
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beq 1f
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cmpwi r0,0x3c
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beq 1f
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cmpwi r0,0x44
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bnelr
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1: /* Before accessing memory, we make sure rm_ci is clear */
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li r0,0
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mfspr r3,SPRN_HID4
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rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
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sync
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mtspr SPRN_HID4,r3
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isync
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sync
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/* Clear interrupt prefix */
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li r0,0
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sync
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mtspr SPRN_HIOR,0
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isync
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/* Restore HID0 */
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ld r3,CS_HID0(r5)
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sync
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isync
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mtspr SPRN_HID0,r3
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mfspr r3,SPRN_HID0
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mfspr r3,SPRN_HID0
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mfspr r3,SPRN_HID0
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mfspr r3,SPRN_HID0
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mfspr r3,SPRN_HID0
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mfspr r3,SPRN_HID0
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sync
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isync
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/* Restore HID1 */
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ld r3,CS_HID1(r5)
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sync
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isync
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mtspr SPRN_HID1,r3
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mtspr SPRN_HID1,r3
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sync
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isync
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/* Restore HID4 */
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ld r3,CS_HID4(r5)
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sync
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isync
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mtspr SPRN_HID4,r3
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sync
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isync
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/* Restore HID5 */
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ld r3,CS_HID5(r5)
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sync
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isync
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mtspr SPRN_HID5,r3
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sync
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isync
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blr
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