46bc858720
The microdev only has to contend with silly PIO mangling on anything within the SuperIO range. As each of the SuperIO modules is already speciail cased, we just shift that logic over to the ioport map. With microdev PCI never being merged (and being fudamentally broken in hardware), and the ethernet chip only doing 16-bit accesses already, there's no need to maintain any of the extra special casing. Kill it all off. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
200 lines
5.6 KiB
C
200 lines
5.6 KiB
C
/*
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* arch/sh/boards/superh/microdev/setup.c
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*
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* Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
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* Copyright (C) 2003, 2004 SuperH, Inc.
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* Copyright (C) 2004, 2005 Paul Mundt
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*
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* SuperH SH4-202 MicroDev board support.
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/ioport.h>
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#include <video/s1d13xxxfb.h>
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#include <mach/microdev.h>
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#include <asm/io.h>
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#include <asm/machvec.h>
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#include <asm/sizes.h>
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static struct resource smc91x_resources[] = {
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[0] = {
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.start = 0x300,
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.end = 0x300 + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = MICRODEV_LINUX_IRQ_ETHERNET,
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.end = MICRODEV_LINUX_IRQ_ETHERNET,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device smc91x_device = {
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.name = "smc91x",
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.id = -1,
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.num_resources = ARRAY_SIZE(smc91x_resources),
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.resource = smc91x_resources,
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};
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static struct s1d13xxxfb_regval s1d13806_initregs[] = {
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{ S1DREG_MISC, 0x00 },
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{ S1DREG_COM_DISP_MODE, 0x00 },
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{ S1DREG_GPIO_CNF0, 0x00 },
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{ S1DREG_GPIO_CNF1, 0x00 },
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{ S1DREG_GPIO_CTL0, 0x00 },
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{ S1DREG_GPIO_CTL1, 0x00 },
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{ S1DREG_CLK_CNF, 0x02 },
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{ S1DREG_LCD_CLK_CNF, 0x01 },
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{ S1DREG_CRT_CLK_CNF, 0x03 },
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{ S1DREG_MPLUG_CLK_CNF, 0x03 },
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{ S1DREG_CPU2MEM_WST_SEL, 0x02 },
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{ S1DREG_SDRAM_REF_RATE, 0x03 },
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{ S1DREG_SDRAM_TC0, 0x00 },
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{ S1DREG_SDRAM_TC1, 0x01 },
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{ S1DREG_MEM_CNF, 0x80 },
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{ S1DREG_PANEL_TYPE, 0x25 },
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{ S1DREG_MOD_RATE, 0x00 },
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{ S1DREG_LCD_DISP_HWIDTH, 0x63 },
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{ S1DREG_LCD_NDISP_HPER, 0x1e },
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{ S1DREG_TFT_FPLINE_START, 0x06 },
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{ S1DREG_TFT_FPLINE_PWIDTH, 0x03 },
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{ S1DREG_LCD_DISP_VHEIGHT0, 0x57 },
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{ S1DREG_LCD_DISP_VHEIGHT1, 0x02 },
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{ S1DREG_LCD_NDISP_VPER, 0x00 },
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{ S1DREG_TFT_FPFRAME_START, 0x0a },
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{ S1DREG_TFT_FPFRAME_PWIDTH, 0x81 },
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{ S1DREG_LCD_DISP_MODE, 0x03 },
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{ S1DREG_LCD_MISC, 0x00 },
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{ S1DREG_LCD_DISP_START0, 0x00 },
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{ S1DREG_LCD_DISP_START1, 0x00 },
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{ S1DREG_LCD_DISP_START2, 0x00 },
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{ S1DREG_LCD_MEM_OFF0, 0x90 },
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{ S1DREG_LCD_MEM_OFF1, 0x01 },
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{ S1DREG_LCD_PIX_PAN, 0x00 },
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{ S1DREG_LCD_DISP_FIFO_HTC, 0x00 },
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{ S1DREG_LCD_DISP_FIFO_LTC, 0x00 },
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{ S1DREG_CRT_DISP_HWIDTH, 0x63 },
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{ S1DREG_CRT_NDISP_HPER, 0x1f },
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{ S1DREG_CRT_HRTC_START, 0x04 },
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{ S1DREG_CRT_HRTC_PWIDTH, 0x8f },
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{ S1DREG_CRT_DISP_VHEIGHT0, 0x57 },
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{ S1DREG_CRT_DISP_VHEIGHT1, 0x02 },
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{ S1DREG_CRT_NDISP_VPER, 0x1b },
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{ S1DREG_CRT_VRTC_START, 0x00 },
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{ S1DREG_CRT_VRTC_PWIDTH, 0x83 },
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{ S1DREG_TV_OUT_CTL, 0x10 },
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{ S1DREG_CRT_DISP_MODE, 0x05 },
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{ S1DREG_CRT_DISP_START0, 0x00 },
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{ S1DREG_CRT_DISP_START1, 0x00 },
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{ S1DREG_CRT_DISP_START2, 0x00 },
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{ S1DREG_CRT_MEM_OFF0, 0x20 },
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{ S1DREG_CRT_MEM_OFF1, 0x03 },
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{ S1DREG_CRT_PIX_PAN, 0x00 },
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{ S1DREG_CRT_DISP_FIFO_HTC, 0x00 },
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{ S1DREG_CRT_DISP_FIFO_LTC, 0x00 },
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{ S1DREG_LCD_CUR_CTL, 0x00 },
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{ S1DREG_LCD_CUR_START, 0x01 },
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{ S1DREG_LCD_CUR_XPOS0, 0x00 },
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{ S1DREG_LCD_CUR_XPOS1, 0x00 },
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{ S1DREG_LCD_CUR_YPOS0, 0x00 },
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{ S1DREG_LCD_CUR_YPOS1, 0x00 },
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{ S1DREG_LCD_CUR_BCTL0, 0x00 },
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{ S1DREG_LCD_CUR_GCTL0, 0x00 },
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{ S1DREG_LCD_CUR_RCTL0, 0x00 },
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{ S1DREG_LCD_CUR_BCTL1, 0x1f },
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{ S1DREG_LCD_CUR_GCTL1, 0x3f },
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{ S1DREG_LCD_CUR_RCTL1, 0x1f },
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{ S1DREG_LCD_CUR_FIFO_HTC, 0x00 },
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{ S1DREG_CRT_CUR_CTL, 0x00 },
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{ S1DREG_CRT_CUR_START, 0x01 },
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{ S1DREG_CRT_CUR_XPOS0, 0x00 },
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{ S1DREG_CRT_CUR_XPOS1, 0x00 },
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{ S1DREG_CRT_CUR_YPOS0, 0x00 },
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{ S1DREG_CRT_CUR_YPOS1, 0x00 },
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{ S1DREG_CRT_CUR_BCTL0, 0x00 },
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{ S1DREG_CRT_CUR_GCTL0, 0x00 },
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{ S1DREG_CRT_CUR_RCTL0, 0x00 },
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{ S1DREG_CRT_CUR_BCTL1, 0x1f },
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{ S1DREG_CRT_CUR_GCTL1, 0x3f },
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{ S1DREG_CRT_CUR_RCTL1, 0x1f },
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{ S1DREG_CRT_CUR_FIFO_HTC, 0x00 },
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{ S1DREG_BBLT_CTL0, 0x00 },
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{ S1DREG_BBLT_CTL1, 0x00 },
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{ S1DREG_BBLT_CC_EXP, 0x00 },
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{ S1DREG_BBLT_OP, 0x00 },
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{ S1DREG_BBLT_SRC_START0, 0x00 },
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{ S1DREG_BBLT_SRC_START1, 0x00 },
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{ S1DREG_BBLT_SRC_START2, 0x00 },
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{ S1DREG_BBLT_DST_START0, 0x00 },
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{ S1DREG_BBLT_DST_START1, 0x00 },
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{ S1DREG_BBLT_DST_START2, 0x00 },
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{ S1DREG_BBLT_MEM_OFF0, 0x00 },
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{ S1DREG_BBLT_MEM_OFF1, 0x00 },
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{ S1DREG_BBLT_WIDTH0, 0x00 },
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{ S1DREG_BBLT_WIDTH1, 0x00 },
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{ S1DREG_BBLT_HEIGHT0, 0x00 },
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{ S1DREG_BBLT_HEIGHT1, 0x00 },
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{ S1DREG_BBLT_BGC0, 0x00 },
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{ S1DREG_BBLT_BGC1, 0x00 },
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{ S1DREG_BBLT_FGC0, 0x00 },
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{ S1DREG_BBLT_FGC1, 0x00 },
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{ S1DREG_LKUP_MODE, 0x00 },
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{ S1DREG_LKUP_ADDR, 0x00 },
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{ S1DREG_PS_CNF, 0x10 },
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{ S1DREG_PS_STATUS, 0x00 },
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{ S1DREG_CPU2MEM_WDOGT, 0x00 },
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{ S1DREG_COM_DISP_MODE, 0x02 },
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};
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static struct s1d13xxxfb_pdata s1d13806_platform_data = {
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.initregs = s1d13806_initregs,
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.initregssize = ARRAY_SIZE(s1d13806_initregs),
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};
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static struct resource s1d13806_resources[] = {
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[0] = {
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.start = 0x07200000,
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.end = 0x07200000 + SZ_2M - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 0x07000000,
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.end = 0x07000000 + SZ_2M - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device s1d13806_device = {
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.name = "s1d13806fb",
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.id = -1,
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.num_resources = ARRAY_SIZE(s1d13806_resources),
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.resource = s1d13806_resources,
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.dev = {
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.platform_data = &s1d13806_platform_data,
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},
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};
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static struct platform_device *microdev_devices[] __initdata = {
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&smc91x_device,
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&s1d13806_device,
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};
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static int __init microdev_devices_setup(void)
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{
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return platform_add_devices(microdev_devices, ARRAY_SIZE(microdev_devices));
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}
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device_initcall(microdev_devices_setup);
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/*
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* The Machine Vector
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*/
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static struct sh_machine_vector mv_sh4202_microdev __initmv = {
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.mv_name = "SH4-202 MicroDev",
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.mv_nr_irqs = 72,
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.mv_ioport_map = microdev_ioport_map,
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.mv_init_irq = init_microdev_irq,
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};
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