ceaed0c809
Moving milestone to soc specific early initcall. This change is to enable kernel memory protection before multi-core bring up, to avoid a race condition between cores. Change-Id: Iaeb6620ed1f5bb89265a2529d15cfbde50a829ee Acked-by: Neeraj Upadhyay <neeraju@codeaurora.org> Signed-off-by: Preeti Nagar <pnagar@codeaurora.org>
170 lines
3.8 KiB
C
170 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2010-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef __MACH_SCM_H
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#define __MACH_SCM_H
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#include <soc/qcom/qtee_shmbridge.h>
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#define SCM_SVC_BOOT 0x1
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#define SCM_SVC_PIL 0x2
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#define SCM_SVC_UTIL 0x3
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#define SCM_SVC_TZ 0x4
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#define SCM_SVC_IO 0x5
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#define SCM_SVC_INFO 0x6
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#define SCM_SVC_SSD 0x7
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#define SCM_SVC_FUSE 0x8
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#define SCM_SVC_PWR 0x9
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#define SCM_SVC_MP 0xC
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#define SCM_SVC_DCVS 0xD
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#define SCM_SVC_ES 0x10
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#define SCM_SVC_HDCP 0x11
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#define SCM_SVC_MDTP 0x12
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#define SCM_SVC_LMH 0x13
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#define SCM_SVC_SMMU_PROGRAM 0x15
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#define SCM_SVC_QDSS 0x16
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#define SCM_SVC_RTIC 0x19
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#define SCM_SVC_TSENS 0x1E
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#define SCM_SVC_TZSCHEDULER 0xFC
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#define SCM_FUSE_READ 0x7
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#define SCM_CMD_HDCP 0x01
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/* SCM Features */
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#define SCM_SVC_SEC_CAMERA 0xD
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#define DEFINE_SCM_BUFFER(__n) \
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static char __n[PAGE_SIZE] __aligned(PAGE_SIZE)
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#define SCM_BUFFER_SIZE(__buf) sizeof(__buf)
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#define SCM_BUFFER_PHYS(__buf) virt_to_phys(__buf)
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#define SCM_SIP_FNID(s, c) (((((s) & 0xFF) << 8) | ((c) & 0xFF)) | 0x02000000)
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#define SCM_QSEEOS_FNID(s, c) (((((s) & 0xFF) << 8) | ((c) & 0xFF)) | \
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0x32000000)
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#define SCM_SVC_ID(s) (((s) & 0xFF00) >> 8)
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#define MAX_SCM_ARGS 10
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#define MAX_SCM_RETS 3
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enum scm_arg_types {
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SCM_VAL,
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SCM_RO,
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SCM_RW,
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SCM_BUFVAL,
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};
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#define SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
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(((a) & 0xff) << 4) | \
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(((b) & 0xff) << 6) | \
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(((c) & 0xff) << 8) | \
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(((d) & 0xff) << 10) | \
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(((e) & 0xff) << 12) | \
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(((f) & 0xff) << 14) | \
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(((g) & 0xff) << 16) | \
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(((h) & 0xff) << 18) | \
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(((i) & 0xff) << 20) | \
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(((j) & 0xff) << 22) | \
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(num & 0xffff))
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#define SCM_ARGS(...) SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
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/**
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* struct scm_desc
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* @arginfo: Metadata describing the arguments in args[]
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* @args: The array of arguments for the secure syscall
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* @ret: The values returned by the secure syscall
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* @extra_arg_buf: The buffer containing extra arguments
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(that don't fit in available registers)
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* @x5: The 4rd argument to the secure syscall or physical address of
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extra_arg_buf
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*/
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struct scm_desc {
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u32 arginfo;
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u64 args[MAX_SCM_ARGS];
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u64 ret[MAX_SCM_RETS];
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/* private */
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struct qtee_shm shm;
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u64 x5;
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};
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#ifdef CONFIG_QCOM_SCM
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#define SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
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extern int scm_call2(u32 cmd_id, struct scm_desc *desc);
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extern int scm_call2_noretry(u32 cmd_id, struct scm_desc *desc);
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extern int scm_call2_atomic(u32 cmd_id, struct scm_desc *desc);
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extern u32 scm_get_version(void);
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extern int scm_is_call_available(u32 svc_id, u32 cmd_id);
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extern int scm_restore_sec_cfg(u32 device_id, u32 spare, int *scm_ret);
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extern u32 scm_io_read(phys_addr_t address);
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extern int scm_io_write(phys_addr_t address, u32 val);
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extern bool scm_is_secure_device(void);
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extern int scm_get_feat_version(u32 feat);
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extern bool is_scm_armv8(void);
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extern struct mutex scm_lmh_lock;
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#else
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static inline int scm_call2(u32 cmd_id, struct scm_desc *desc)
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{
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return 0;
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}
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static inline int scm_call2_noretry(u32 cmd_id, struct scm_desc *desc)
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{
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return 0;
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}
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static inline int scm_call2_atomic(u32 cmd_id, struct scm_desc *desc)
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{
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return 0;
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}
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static inline u32 scm_get_version(void)
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{
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return 0;
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}
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static inline int scm_get_feat_version(u32 feat)
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{
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return 0;
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}
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static inline int scm_is_call_available(u32 svc_id, u32 cmd_id)
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{
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return 0;
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}
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static inline bool is_scm_armv8(void)
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{
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return true;
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}
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static inline int scm_restore_sec_cfg(u32 device_id, u32 spare, int *scm_ret)
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{
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return 0;
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}
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static inline u32 scm_io_read(phys_addr_t address)
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{
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return 0;
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}
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static inline int scm_io_write(phys_addr_t address, u32 val)
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{
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return 0;
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}
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static inline bool scm_is_secure_device(void)
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{
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return false;
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}
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#endif
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#endif
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