257 lines
8.3 KiB
C
257 lines
8.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef __MSM_GPI_H_
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#define __MSM_GPI_H_
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struct __packed msm_gpi_tre {
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u32 dword[4];
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};
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enum msm_gpi_tre_type {
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MSM_GPI_TRE_INVALID = 0x00,
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MSM_GPI_TRE_NOP = 0x01,
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MSM_GPI_TRE_DMA_W_BUF = 0x10,
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MSM_GPI_TRE_DMA_IMMEDIATE = 0x11,
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MSM_GPI_TRE_DMA_W_SG_LIST = 0x12,
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MSM_GPI_TRE_GO = 0x20,
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MSM_GPI_TRE_CONFIG0 = 0x22,
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MSM_GPI_TRE_CONFIG1 = 0x23,
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MSM_GPI_TRE_CONFIG2 = 0x24,
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MSM_GPI_TRE_CONFIG3 = 0x25,
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MSM_GPI_TRE_LOCK = 0x30,
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MSM_GPI_TRE_UNLOCK = 0x31,
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};
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#define MSM_GPI_TRE_TYPE(tre) ((tre->dword[3] >> 16) & 0xFF)
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/* Lock TRE */
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#define MSM_GPI_LOCK_TRE_DWORD0 (0)
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#define MSM_GPI_LOCK_TRE_DWORD1 (0)
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#define MSM_GPI_LOCK_TRE_DWORD2 (0)
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#define MSM_GPI_LOCK_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
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((0x3 << 20) | (0x0 << 16) | (link_rx << 11) | (bei << 10) | \
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(ieot << 9) | (ieob << 8) | ch)
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/* Unlock TRE */
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#define MSM_GPI_UNLOCK_TRE_DWORD0 (0)
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#define MSM_GPI_UNLOCK_TRE_DWORD1 (0)
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#define MSM_GPI_UNLOCK_TRE_DWORD2 (0)
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#define MSM_GPI_UNLOCK_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
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((0x3 << 20) | (0x1 << 16) | (link_rx << 11) | (bei << 10) | \
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(ieot << 9) | (ieob << 8) | ch)
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/* DMA w. Buffer TRE */
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#ifdef CONFIG_ARM64
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#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD0(ptr) ((u32)ptr)
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#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD1(ptr) ((u32)(ptr >> 32))
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#else
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#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD0(ptr) (ptr)
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#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD1(ptr) 0
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#endif
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#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD2(length) (length & 0xFFFFFF)
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#define MSM_GPI_DMA_W_BUFFER_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
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((0x1 << 20) | (0x0 << 16) | (link_rx << 11) | (bei << 10) | \
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(ieot << 9) | (ieob << 8) | ch)
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#define MSM_GPI_DMA_W_BUFFER_TRE_GET_LEN(tre) (tre->dword[2] & 0xFFFFFF)
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#define MSM_GPI_DMA_W_BUFFER_TRE_SET_LEN(tre, length) (tre->dword[2] = \
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MSM_GPI_DMA_W_BUFFER_TRE_DWORD2(length))
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/* DMA Immediate TRE */
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#define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD0(d3, d2, d1, d0) ((d3 << 24) | \
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(d2 << 16) | (d1 << 8) | (d0))
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#define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD1(d4, d5, d6, d7) ((d7 << 24) | \
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(d6 << 16) | (d5 << 8) | (d4))
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#define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD2(length) (length & 0xF)
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#define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
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((0x1 << 20) | (0x1 << 16) | (link_rx << 11) | (bei << 10) | \
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(ieot << 9) | (ieob << 8) | ch)
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#define MSM_GPI_DMA_IMMEDIATE_TRE_GET_LEN(tre) (tre->dword[2] & 0xF)
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/* DMA w. Scatter/Gather List TRE */
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#ifdef CONFIG_ARM64
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#define MSM_GPI_SG_LIST_TRE_DWORD0(ptr) ((u32)ptr)
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#define MSM_GPI_SG_LIST_TRE_DWORD1(ptr) ((u32)(ptr >> 32))
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#else
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#define MSM_GPI_SG_LIST_TRE_DWORD0(ptr) (ptr)
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#define MSM_GPI_SG_LIST_TRE_DWORD1(ptr) 0
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#endif
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#define MSM_GPI_SG_LIST_TRE_DWORD2(length) (length & 0xFFFF)
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#define MSM_GPI_SG_LIST_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x1 << 20) \
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| (0x2 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
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(ieob << 8) | ch)
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/* SG Element */
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#ifdef CONFIG_ARM64
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#define MSM_GPI_SG_ELEMENT_DWORD0(ptr) ((u32)ptr)
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#define MSM_GPI_SG_ELEMENT_DWORD1(ptr) ((u32)(ptr >> 32))
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#else
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#define MSM_GPI_SG_ELEMENT_DWORD0(ptr) (ptr)
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#define MSM_GPI_SG_ELEMENT_DWORD1(ptr) 0
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#endif
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#define MSM_GSI_SG_ELEMENT_DWORD2(length) (length & 0xFFFFF)
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#define MSM_GSI_SG_ELEMENT_DWORD3 (0)
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/* Config2 TRE */
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#define GPI_CONFIG2_TRE_DWORD0(gr, txp) ((gr << 20) | (txp))
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#define GPI_CONFIG2_TRE_DWORD1(txp) (txp)
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#define GPI_CONFIG2_TRE_DWORD2 (0)
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#define GPI_CONFIG2_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) | \
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(0x4 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
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(ieob << 8) | ch)
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/* Config3 TRE */
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#define GPI_CONFIG3_TRE_DWORD0(rxp) (rxp)
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#define GPI_CONFIG3_TRE_DWORD1(rxp) (rxp)
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#define GPI_CONFIG3_TRE_DWORD2 (0)
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#define GPI_CONFIG3_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) \
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| (0x5 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
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(ieob << 8) | ch)
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/* SPI Go TRE */
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#define MSM_GPI_SPI_GO_TRE_DWORD0(flags, cs, command) ((flags << 24) | \
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(cs << 8) | command)
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#define MSM_GPI_SPI_GO_TRE_DWORD1 (0)
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#define MSM_GPI_SPI_GO_TRE_DWORD2(rx_len) (rx_len)
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#define MSM_GPI_SPI_GO_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) | \
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(0x0 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
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(ieob << 8) | ch)
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/* SPI Config0 TRE */
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#define MSM_GPI_SPI_CONFIG0_TRE_DWORD0(pack, flags, word_size) ((pack << 24) | \
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(flags << 8) | word_size)
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#define MSM_GPI_SPI_CONFIG0_TRE_DWORD1(it_del, cs_clk_del, iw_del) \
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((it_del << 16) | (cs_clk_del << 8) | iw_del)
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#define MSM_GPI_SPI_CONFIG0_TRE_DWORD2(clk_src, clk_div) ((clk_src << 16) | \
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clk_div)
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#define MSM_GPI_SPI_CONFIG0_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
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((0x2 << 20) | (0x2 << 16) | (link_rx << 11) | (bei << 10) | \
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(ieot << 9) | (ieob << 8) | ch)
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/* UART Go TRE */
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#define MSM_GPI_UART_GO_TRE_DWORD0(en_hunt, command) ((en_hunt << 8) | command)
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#define MSM_GPI_UART_GO_TRE_DWORD1 (0)
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#define MSM_GPI_UART_GO_TRE_DWORD2 (0)
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#define MSM_GPI_UART_GO_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) \
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| (0x0 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
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(ieob << 8) | ch)
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/* UART Config0 TRE */
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#define MSM_GPI_UART_CONFIG0_TRE_DWORD0(pack, hunt, flags, parity, sbl, size) \
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((pack << 24) | (hunt << 16) | (flags << 8) | (parity << 5) | \
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(sbl << 3) | size)
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#define MSM_GPI_UART_CONFIG0_TRE_DWORD1(rfr_level, rx_stale) \
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((rfr_level << 24) | rx_stale)
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#define MSM_GPI_UART_CONFIG0_TRE_DWORD2(clk_source, clk_div) \
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((clk_source << 16) | clk_div)
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#define MSM_GPI_UART_CONFIG0_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
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((0x2 << 20) | (0x2 << 16) | (link_rx << 11) | (bei << 10) | \
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(ieot << 9) | (ieob << 8) | ch)
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/* I2C GO TRE */
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#define MSM_GPI_I2C_GO_TRE_DWORD0(flags, slave, opcode) \
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((flags << 24) | (slave << 8) | opcode)
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#define MSM_GPI_I2C_GO_TRE_DWORD1 (0)
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#define MSM_GPI_I2C_GO_TRE_DWORD2(rx_len) (rx_len)
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#define MSM_GPI_I2C_GO_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) | \
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(0x0 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
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(ieob << 8) | ch)
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/* I2C Config0 TRE */
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#define MSM_GPI_I2C_CONFIG0_TRE_DWORD0(pack, t_cycle, t_high, t_low) \
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((pack << 24) | (t_cycle << 16) | (t_high << 8) | t_low)
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#define MSM_GPI_I2C_CONFIG0_TRE_DWORD1(inter_delay, noise_rej) \
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((inter_delay << 16) | noise_rej)
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#define MSM_GPI_I2C_CONFIG0_TRE_DWORD2(clk_src, clk_div) \
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((clk_src << 16) | clk_div)
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#define MSM_GPI_I2C_CONFIG0_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
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((0x2 << 20) | (0x2 << 16) | (link_rx << 11) | (bei << 10) | \
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(ieot << 9) | (ieob << 8) | ch)
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#ifdef CONFIG_ARM64
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#define MSM_GPI_RING_PHYS_ADDR_UPPER(ptr) ((u32)(ptr >> 32))
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#else
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#define MSM_GPI_RING_PHYS_ADDR_UPPER(ptr) 0
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#endif
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/* cmds to perform by using dmaengine_slave_config() */
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enum msm_gpi_ctrl_cmd {
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MSM_GPI_INIT,
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MSM_GPI_CMD_UART_SW_STALE,
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MSM_GPI_CMD_UART_RFR_READY,
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MSM_GPI_CMD_UART_RFR_NOT_READY,
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};
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enum msm_gpi_cb_event {
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/* These events are hardware generated events */
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MSM_GPI_QUP_NOTIFY,
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MSM_GPI_QUP_ERROR, /* global error */
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MSM_GPI_QUP_CH_ERROR, /* channel specific error */
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MSM_GPI_QUP_FW_ERROR, /* unhandled error */
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/* These events indicate a software bug */
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MSM_GPI_QUP_PENDING_EVENT,
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MSM_GPI_QUP_EOT_DESC_MISMATCH,
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MSM_GPI_QUP_SW_ERROR,
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MSM_GPI_QUP_MAX_EVENT,
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};
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struct msm_gpi_error_log {
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u32 routine;
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u32 type;
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u32 error_code;
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};
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struct msm_gpi_cb {
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enum msm_gpi_cb_event cb_event;
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u64 status;
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u64 timestamp;
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u64 count;
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struct msm_gpi_error_log error_log;
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};
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struct gpi_client_info {
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/*
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* memory for msm_gpi_cb is released after callback, clients shall
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* save any required data for post processing after returning
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* from callback
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*/
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void (*callback)(struct dma_chan *chan,
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struct msm_gpi_cb const *msm_gpi_cb,
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void *cb_param);
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void *cb_param;
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};
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/*
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* control structure to config gpi dma engine via dmaengine_slave_config()
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* dma_chan.private should point to msm_gpi_ctrl structure
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*/
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struct msm_gpi_ctrl {
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enum msm_gpi_ctrl_cmd cmd;
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union {
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struct gpi_client_info init;
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};
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};
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enum msm_gpi_tce_code {
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MSM_GPI_TCE_SUCCESS = 1,
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MSM_GPI_TCE_EOT = 2,
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MSM_GPI_TCE_EOB = 4,
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MSM_GPI_TCE_UNEXP_ERR = 16,
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};
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/*
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* gpi specific callback parameters to pass between gpi client and gpi engine.
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* client shall set async_desc.callback_parm to msm_gpi_dma_async_tx_cb_param
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*/
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struct msm_gpi_dma_async_tx_cb_param {
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u32 length;
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enum msm_gpi_tce_code completion_code; /* TCE event code */
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u32 status;
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struct __packed msm_gpi_tre imed_tre;
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void *userdata;
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};
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#endif
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