kernel-fxtec-pro1x/Documentation/perf
Mukesh Ojha 5745954a5a perf: add qcom l2 cache perf events driver
The L2 cache perf driver is named 'l2cache_counters' and can be
used with perf tool to profile L2 cache events as below

=> DDR read (Read-Shared, Read-Unique, Read-Clean and
   Read-Not-Shared-Dirty transactions on GNOC Interface)

=> DDR write (Write-Back, Write-Clean and Write-Evict transactions
   on GNOC Interface

=> SNOOP Read (Read-Once, Read-Shared, Read-Unique, Read-Clean and
   Read-Not-Shared-Dirty transactions from GNOC to Cluster interface)

=> ACP Write(Write-Back, Write-Clean and Write-Evict transactions
   to ACP port of Collapsed Cluster)

=> Tenure counter(Low-Power mode tenure is used to count tenure (no. of XO-
   19.2MHz) of L2 Low-Power mode.

=> Low/Mid/High occurrence counter: Based on threshold set for low and mid
   tenure counter, current tenure count is compared and based on which
   category it belongs, respective occurrence counter gets incremented.
   e.g:

   1. 0 < Current Tenure <= Low-tenure threshold : Low-Tenure
   2. Low-tenure < Current Tenure <= Mid-tenure threshold : Mid-Tenure
   3. Mid-tenure < Current tenure : High-Tenure

Change-Id: I9f8aedd21a92cbd6908deb5a8e4c7e32220bea74
Signed-off-by: Mukesh Ojha <mojha@codeaurora.org>
2019-12-26 12:45:54 +05:30
..
arm-ccn.txt drivers/bus: Move Arm CCN PMU driver 2018-03-06 17:26:15 +01:00
arm_dsu_pmu.txt perf: ARM DynamIQ Shared Unit PMU support 2018-01-02 16:43:12 +00:00
hisi-pmu.txt Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver 2017-10-19 17:06:34 +01:00
qcom_l2_counters.txt perf: add qcom l2 cache perf events driver 2019-12-26 12:45:54 +05:30
qcom_l2_pmu.txt
qcom_l3_pmu.txt perf: qcom: Add L3 cache PMU driver 2017-04-03 18:53:50 +01:00
xgene-pmu.txt