9301975ec2
This merges branches irq/genirq, irq/sparseirq-v4, timers/hpet-percpu and x86/uv. The sparseirq branch is just preliminary groundwork: no sparse IRQs are actually implemented by this tree anymore - just the new APIs are added while keeping the old way intact as well (the new APIs map 1:1 to irq_desc[]). The 'real' sparse IRQ support will then be a relatively small patch ontop of this - with a v2.6.29 merge target. * 'genirq-v28-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (178 commits) genirq: improve include files intr_remapping: fix typo io_apic: make irq_mis_count available on 64-bit too genirq: fix name space collisions of nr_irqs in arch/* genirq: fix name space collision of nr_irqs in autoprobe.c genirq: use iterators for irq_desc loops proc: fixup irq iterator genirq: add reverse iterator for irq_desc x86: move ack_bad_irq() to irq.c x86: unify show_interrupts() and proc helpers x86: cleanup show_interrupts genirq: cleanup the sparseirq modifications genirq: remove artifacts from sparseirq removal genirq: revert dynarray genirq: remove irq_to_desc_alloc genirq: remove sparse irq code genirq: use inline function for irq_to_desc genirq: consolidate nr_irqs and for_each_irq_desc() x86: remove sparse irq from Kconfig genirq: define nr_irqs for architectures with GENERIC_HARDIRQS=n ...
149 lines
3.6 KiB
C
149 lines
3.6 KiB
C
/*
|
|
* linux/arch/arm/mach-omap2/irq.c
|
|
*
|
|
* Interrupt handler for OMAP2 boards.
|
|
*
|
|
* Copyright (C) 2005 Nokia Corporation
|
|
* Author: Paul Mundt <paul.mundt@nokia.com>
|
|
*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*/
|
|
#include <linux/kernel.h>
|
|
#include <linux/init.h>
|
|
#include <linux/interrupt.h>
|
|
#include <linux/io.h>
|
|
#include <mach/hardware.h>
|
|
#include <asm/mach/irq.h>
|
|
|
|
|
|
/* selected INTC register offsets */
|
|
|
|
#define INTC_REVISION 0x0000
|
|
#define INTC_SYSCONFIG 0x0010
|
|
#define INTC_SYSSTATUS 0x0014
|
|
#define INTC_CONTROL 0x0048
|
|
#define INTC_MIR_CLEAR0 0x0088
|
|
#define INTC_MIR_SET0 0x008c
|
|
#define INTC_PENDING_IRQ0 0x0098
|
|
|
|
/* Number of IRQ state bits in each MIR register */
|
|
#define IRQ_BITS_PER_REG 32
|
|
|
|
/*
|
|
* OMAP2 has a number of different interrupt controllers, each interrupt
|
|
* controller is identified as its own "bank". Register definitions are
|
|
* fairly consistent for each bank, but not all registers are implemented
|
|
* for each bank.. when in doubt, consult the TRM.
|
|
*/
|
|
static struct omap_irq_bank {
|
|
void __iomem *base_reg;
|
|
unsigned int nr_irqs;
|
|
} __attribute__ ((aligned(4))) irq_banks[] = {
|
|
{
|
|
/* MPU INTC */
|
|
.base_reg = 0,
|
|
.nr_irqs = 96,
|
|
},
|
|
};
|
|
|
|
/* INTC bank register get/set */
|
|
|
|
static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
|
|
{
|
|
__raw_writel(val, bank->base_reg + reg);
|
|
}
|
|
|
|
static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
|
|
{
|
|
return __raw_readl(bank->base_reg + reg);
|
|
}
|
|
|
|
/* XXX: FIQ and additional INTC support (only MPU at the moment) */
|
|
static void omap_ack_irq(unsigned int irq)
|
|
{
|
|
intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
|
|
}
|
|
|
|
static void omap_mask_irq(unsigned int irq)
|
|
{
|
|
int offset = irq & (~(IRQ_BITS_PER_REG - 1));
|
|
|
|
irq &= (IRQ_BITS_PER_REG - 1);
|
|
|
|
intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
|
|
}
|
|
|
|
static void omap_unmask_irq(unsigned int irq)
|
|
{
|
|
int offset = irq & (~(IRQ_BITS_PER_REG - 1));
|
|
|
|
irq &= (IRQ_BITS_PER_REG - 1);
|
|
|
|
intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
|
|
}
|
|
|
|
static void omap_mask_ack_irq(unsigned int irq)
|
|
{
|
|
omap_mask_irq(irq);
|
|
omap_ack_irq(irq);
|
|
}
|
|
|
|
static struct irq_chip omap_irq_chip = {
|
|
.name = "INTC",
|
|
.ack = omap_mask_ack_irq,
|
|
.mask = omap_mask_irq,
|
|
.unmask = omap_unmask_irq,
|
|
};
|
|
|
|
static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
|
|
{
|
|
unsigned long tmp;
|
|
|
|
tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
|
|
printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
|
|
"(revision %ld.%ld) with %d interrupts\n",
|
|
bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
|
|
|
|
tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
|
|
tmp |= 1 << 1; /* soft reset */
|
|
intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
|
|
|
|
while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
|
|
/* Wait for reset to complete */;
|
|
|
|
/* Enable autoidle */
|
|
intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
|
|
}
|
|
|
|
void __init omap_init_irq(void)
|
|
{
|
|
unsigned long nr_of_irqs = 0;
|
|
unsigned int nr_banks = 0;
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
|
|
struct omap_irq_bank *bank = irq_banks + i;
|
|
|
|
if (cpu_is_omap24xx())
|
|
bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
|
|
else if (cpu_is_omap34xx())
|
|
bank->base_reg = OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE);
|
|
|
|
omap_irq_bank_init_one(bank);
|
|
|
|
nr_of_irqs += bank->nr_irqs;
|
|
nr_banks++;
|
|
}
|
|
|
|
printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
|
|
nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
|
|
|
|
for (i = 0; i < nr_of_irqs; i++) {
|
|
set_irq_chip(i, &omap_irq_chip);
|
|
set_irq_handler(i, handle_level_irq);
|
|
set_irq_flags(i, IRQF_VALID);
|
|
}
|
|
}
|
|
|