1fc593feaf
The head-v7.S contains a call to the generic cpu_suspend function, which is only available when selected by the i.MX6 code. As pointed out by Shawn Guo, i.MX5 does not actually use any functions defined in head-v7.S. It is also needed only for the i.MX6 power management code and for the SMP code, so we can restrict building this file to situations in which at least one of those two is present. Finally, other platforms with a similar file call it headsmp.S, so we can rename it to the same for consistency. Without this patch, building imx5 standalone results in: arch/arm/mach-imx/built-in.o: In function `v7_cpu_resume': arch/arm/mach-imx/head-v7.S:104: undefined reference to `cpu_resume' Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Cc: Eric Miao <eric.miao@linaro.org> Cc: stable@vger.kernel.org
106 lines
2.7 KiB
ArmAsm
106 lines
2.7 KiB
ArmAsm
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/asm-offsets.h>
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#include <asm/hardware/cache-l2x0.h>
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.section ".text.head", "ax"
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/*
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* The secondary kernel init calls v7_flush_dcache_all before it enables
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* the L1; however, the L1 comes out of reset in an undefined state, so
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* the clean + invalidate performed by v7_flush_dcache_all causes a bunch
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* of cache lines with uninitialized data and uninitialized tags to get
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* written out to memory, which does really unpleasant things to the main
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* processor. We fix this by performing an invalidate, rather than a
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* clean + invalidate, before jumping into the kernel.
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*
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* This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
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* to be called for both secondary cores startup and primary core resume
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* procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S.
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*/
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ENTRY(v7_invalidate_l1)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 2, r0, c0, c0, 0
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mrc p15, 1, r0, c0, c0, 0
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ldr r1, =0x7fff
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and r2, r1, r0, lsr #13
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ldr r1, =0x3ff
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and r3, r1, r0, lsr #3 @ NumWays - 1
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add r2, r2, #1 @ NumSets
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and r0, r0, #0x7
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add r0, r0, #4 @ SetShift
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clz r1, r3 @ WayShift
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add r4, r3, #1 @ NumWays
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1: sub r2, r2, #1 @ NumSets--
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mov r3, r4 @ Temp = NumWays
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2: subs r3, r3, #1 @ Temp--
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mov r5, r3, lsl r1
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mov r6, r2, lsl r0
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orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
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mcr p15, 0, r5, c7, c6, 2
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bgt 2b
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cmp r2, #0
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bgt 1b
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dsb
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isb
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mov pc, lr
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ENDPROC(v7_invalidate_l1)
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#ifdef CONFIG_SMP
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ENTRY(v7_secondary_startup)
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bl v7_invalidate_l1
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b secondary_startup
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ENDPROC(v7_secondary_startup)
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#endif
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#ifdef CONFIG_PM
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/*
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* The following code is located into the .data section. This is to
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* allow phys_l2x0_saved_regs to be accessed with a relative load
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* as we are running on physical address here.
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*/
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.data
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.align
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#ifdef CONFIG_CACHE_L2X0
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.macro pl310_resume
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ldr r2, phys_l2x0_saved_regs
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ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0
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ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value
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str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl
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mov r1, #0x1
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str r1, [r0, #L2X0_CTRL] @ re-enable L2
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.endm
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.globl phys_l2x0_saved_regs
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phys_l2x0_saved_regs:
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.long 0
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#else
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.macro pl310_resume
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.endm
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#endif
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ENTRY(v7_cpu_resume)
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bl v7_invalidate_l1
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pl310_resume
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b cpu_resume
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ENDPROC(v7_cpu_resume)
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#endif
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