5225cd8079
The transition latency has to be defined and reasonably small to allow on-demand and conservative governors. The value has been defined according to manual. The imx_set_target() protected against seen out of range requests now. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
299 lines
7 KiB
C
299 lines
7 KiB
C
/*
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* cpu.c: clock scaling for the iMX
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*
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* Copyright (C) 2000 2001, The Delft University of Technology
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* Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
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* Copyright (C) 2006 Inky Lung <ilung@cwlinux.com>
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* Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
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*
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* Based on SA1100 version written by:
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* - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version
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* - Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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/*#define DEBUG*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <asm/system.h>
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#include <asm/hardware.h>
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#include "generic.h"
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#ifndef __val2mfld
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#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
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#endif
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#ifndef __mfld2val
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#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
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#endif
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#define CR_920T_CLOCK_MODE 0xC0000000
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#define CR_920T_FASTBUS_MODE 0x00000000
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#define CR_920T_ASYNC_MODE 0xC0000000
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static u32 mpctl0_at_boot;
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static void imx_set_async_mode(void)
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{
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adjust_cr(CR_920T_CLOCK_MODE, CR_920T_ASYNC_MODE);
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}
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static void imx_set_fastbus_mode(void)
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{
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adjust_cr(CR_920T_CLOCK_MODE, CR_920T_FASTBUS_MODE);
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}
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static void imx_set_mpctl0(u32 mpctl0)
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{
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unsigned long flags;
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if (mpctl0 == 0) {
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local_irq_save(flags);
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CSCR &= ~CSCR_MPEN;
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local_irq_restore(flags);
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return;
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}
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local_irq_save(flags);
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MPCTL0 = mpctl0;
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CSCR |= CSCR_MPEN;
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local_irq_restore(flags);
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}
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/**
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* imx_compute_mpctl - compute new PLL parameters
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* @new_mpctl: pointer to location assigned by new PLL control register value
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* @cur_mpctl: current PLL control register parameters
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* @freq: required frequency in Hz
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* @relation: is one of %CPUFREQ_RELATION_L (supremum)
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* and %CPUFREQ_RELATION_H (infimum)
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*/
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long imx_compute_mpctl(u32 *new_mpctl, u32 cur_mpctl, unsigned long freq, int relation)
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{
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u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512);
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u32 mfi;
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u32 mfn;
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u32 mfd;
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u32 pd;
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unsigned long long ll;
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long l;
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long quot;
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/* Fdppl=2*Fref*(MFI+MFN/(MFD+1))/(PD+1) */
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/* PD=<0,15>, MFD=<1,1023>, MFI=<5,15> MFN=<0,1022> */
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if (cur_mpctl) {
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mfd = ((cur_mpctl >> 16) & 0x3ff) + 1;
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pd = ((cur_mpctl >> 26) & 0xf) + 1;
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} else {
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pd=2; mfd=313;
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}
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/* pd=2; mfd=313; mfi=8; mfn=183; */
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/* (MFI+MFN/(MFD)) = Fdppl / (2*Fref) * (PD); */
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quot = (f_ref + (1 << 9)) >> 10;
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l = (freq * pd + quot) / (2 * quot);
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mfi = l >> 10;
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mfn = ((l & ((1 << 10) - 1)) * mfd + (1 << 9)) >> 10;
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mfd -= 1;
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pd -= 1;
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*new_mpctl = ((mfi & 0xf) << 10) | (mfn & 0x3ff) | ((mfd & 0x3ff) << 16)
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| ((pd & 0xf) << 26);
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ll = 2 * (unsigned long long)f_ref * ( (mfi<<16) + (mfn<<16) / (mfd+1) );
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quot = (pd+1) * (1<<16);
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ll += quot / 2;
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do_div(ll, quot);
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freq = ll;
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pr_debug(KERN_DEBUG "imx: new PLL parameters pd=%d mfd=%d mfi=%d mfn=%d, freq=%ld\n",
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pd, mfd, mfi, mfn, freq);
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return freq;
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}
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static int imx_verify_speed(struct cpufreq_policy *policy)
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{
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if (policy->cpu != 0)
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return -EINVAL;
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cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
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return 0;
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}
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static unsigned int imx_get_speed(unsigned int cpu)
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{
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unsigned int freq;
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unsigned int cr;
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unsigned int cscr;
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unsigned int bclk_div;
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if (cpu)
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return 0;
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cscr = CSCR;
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bclk_div = __mfld2val(CSCR_BCLK_DIV, cscr) + 1;
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cr = get_cr();
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if((cr & CR_920T_CLOCK_MODE) == CR_920T_FASTBUS_MODE) {
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freq = imx_get_system_clk();
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freq = (freq + bclk_div/2) / bclk_div;
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} else {
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freq = imx_get_mcu_clk();
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if (cscr & CSCR_MPU_PRESC)
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freq /= 2;
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}
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freq = (freq + 500) / 1000;
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return freq;
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}
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static int imx_set_target(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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{
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struct cpufreq_freqs freqs;
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u32 mpctl0 = 0;
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u32 cscr;
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unsigned long flags;
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long freq;
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long sysclk;
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unsigned int bclk_div = 1;
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/*
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* Some governors do not respects CPU and policy lower limits
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* which leads to bad things (division by zero etc), ensure
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* that such things do not happen.
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*/
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if(target_freq < policy->cpuinfo.min_freq)
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target_freq = policy->cpuinfo.min_freq;
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if(target_freq < policy->min)
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target_freq = policy->min;
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freq = target_freq * 1000;
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pr_debug(KERN_DEBUG "imx: requested frequency %ld Hz, mpctl0 at boot 0x%08x\n",
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freq, mpctl0_at_boot);
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sysclk = imx_get_system_clk();
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if (freq > sysclk + 1000000) {
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freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, freq, relation);
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if (freq < 0) {
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printk(KERN_WARNING "imx: target frequency %ld Hz cannot be set\n", freq);
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return -EINVAL;
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}
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} else {
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if(freq + 1000 < sysclk) {
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if (relation == CPUFREQ_RELATION_L)
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bclk_div = (sysclk - 1000) / freq;
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else
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bclk_div = (sysclk + freq + 1000) / freq;
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if(bclk_div > 16)
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bclk_div = 16;
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}
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freq = (sysclk + bclk_div / 2) / bclk_div;
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}
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freqs.old = imx_get_speed(0);
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freqs.new = (freq + 500) / 1000;
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freqs.cpu = 0;
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freqs.flags = 0;
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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local_irq_save(flags);
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imx_set_fastbus_mode();
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imx_set_mpctl0(mpctl0);
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cscr = CSCR;
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cscr &= ~CSCR_BCLK_DIV;
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cscr |= __val2mfld(CSCR_BCLK_DIV, bclk_div - 1);
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CSCR = cscr;
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if(mpctl0) {
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CSCR |= CSCR_MPLL_RESTART;
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/* Wait until MPLL is stablized */
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while( CSCR & CSCR_MPLL_RESTART );
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imx_set_async_mode();
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}
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local_irq_restore(flags);
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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pr_debug(KERN_INFO "imx: set frequency %ld Hz, running from %s\n",
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freq, mpctl0? "MPLL": "SPLL");
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return 0;
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}
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static int __init imx_cpufreq_driver_init(struct cpufreq_policy *policy)
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{
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printk(KERN_INFO "i.MX cpu freq change driver v1.0\n");
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if (policy->cpu != 0)
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return -EINVAL;
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policy->cur = policy->min = policy->max = imx_get_speed(0);
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policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
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policy->cpuinfo.min_freq = 8000;
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policy->cpuinfo.max_freq = 200000;
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/* Manual states, that PLL stabilizes in two CLK32 periods */
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policy->cpuinfo.transition_latency = 4 * 1000000000LL / CLK32;
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return 0;
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}
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static struct cpufreq_driver imx_driver = {
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.flags = CPUFREQ_STICKY,
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.verify = imx_verify_speed,
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.target = imx_set_target,
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.get = imx_get_speed,
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.init = imx_cpufreq_driver_init,
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.name = "imx",
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};
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static int __init imx_cpufreq_init(void)
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{
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mpctl0_at_boot = 0;
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if((CSCR & CSCR_MPEN) &&
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((get_cr() & CR_920T_CLOCK_MODE) != CR_920T_FASTBUS_MODE))
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mpctl0_at_boot = MPCTL0;
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return cpufreq_register_driver(&imx_driver);
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}
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arch_initcall(imx_cpufreq_init);
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