b920de1b77
Add architecture support for the MN10300/AM33 CPUs produced by MEI to the kernel. This patch also adds board support for the ASB2303 with the ASB2308 daughter board, and the ASB2305. The only processor supported is the MN103E010, which is an AM33v2 core plus on-chip devices. [akpm@linux-foundation.org: nuke cvs control strings] Signed-off-by: Masakazu Urade <urade.masakazu@jp.panasonic.com> Signed-off-by: Koichi Yasutake <yasutake.koichi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
33 lines
1.3 KiB
C
33 lines
1.3 KiB
C
/* MN103E010 Cache specification
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#ifndef _ASM_PROC_CACHE_H
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#define _ASM_PROC_CACHE_H
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/* L1 cache */
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#define L1_CACHE_NWAYS 4 /* number of ways in caches */
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#define L1_CACHE_NENTRIES 256 /* number of entries in each way */
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#define L1_CACHE_BYTES 16 /* bytes per entry */
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#define L1_CACHE_SHIFT 4 /* shift for bytes per entry */
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#define L1_CACHE_WAYDISP 0x1000 /* displacement of one way from the next */
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#define L1_CACHE_TAG_VALID 0x00000001 /* cache tag valid bit */
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#define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */
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#define L1_CACHE_TAG_ENTRY 0x00000ff0 /* cache tag entry address mask */
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#define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */
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/*
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* specification of the interval between interrupt checking intervals whilst
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* managing the cache with the interrupts disabled
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*/
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#define MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL 4
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#endif /* _ASM_PROC_CACHE_H */
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