2d1c645cc5
Add support for dispatching medium-priority interrupts, that is, interrupts of priority levels 2 to EXCM_LEVEL. IRQ handling may be preempted by higher priority IRQ. Signed-off-by: Marc Gauthier <marc@tensilica.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
725 lines
16 KiB
C
725 lines
16 KiB
C
/*
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* arch/xtensa/kernel/setup.c
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995 Linus Torvalds
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*
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* Chris Zankel <chris@zankel.net>
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* Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
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* Kevin Chea
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* Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/proc_fs.h>
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#include <linux/screen_info.h>
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#include <linux/bootmem.h>
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#include <linux/kernel.h>
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#ifdef CONFIG_OF
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#include <linux/of_fdt.h>
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#include <linux/of_platform.h>
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#endif
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#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
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# include <linux/console.h>
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#endif
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#ifdef CONFIG_RTC
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# include <linux/timex.h>
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#endif
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#ifdef CONFIG_PROC_FS
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# include <linux/seq_file.h>
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#endif
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#include <asm/bootparam.h>
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#include <asm/pgtable.h>
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#include <asm/processor.h>
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#include <asm/timex.h>
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#include <asm/platform.h>
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#include <asm/page.h>
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#include <asm/setup.h>
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#include <asm/param.h>
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#include <asm/traps.h>
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#include <platform/hardware.h>
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#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
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struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
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#endif
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#ifdef CONFIG_BLK_DEV_FD
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extern struct fd_ops no_fd_ops;
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struct fd_ops *fd_ops;
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#endif
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extern struct rtc_ops no_rtc_ops;
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struct rtc_ops *rtc_ops;
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#ifdef CONFIG_BLK_DEV_INITRD
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extern void *initrd_start;
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extern void *initrd_end;
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int initrd_is_mapped = 0;
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extern int initrd_below_start_ok;
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#endif
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#ifdef CONFIG_OF
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extern u32 __dtb_start[];
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void *dtb_start = __dtb_start;
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#endif
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unsigned char aux_device_present;
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extern unsigned long loops_per_jiffy;
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/* Command line specified as configuration option. */
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static char __initdata command_line[COMMAND_LINE_SIZE];
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#ifdef CONFIG_CMDLINE_BOOL
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static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
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#endif
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sysmem_info_t __initdata sysmem;
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#ifdef CONFIG_MMU
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extern void init_mmu(void);
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#else
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static inline void init_mmu(void) { }
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#endif
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extern int mem_reserve(unsigned long, unsigned long, int);
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extern void bootmem_init(void);
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extern void zones_init(void);
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/*
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* Boot parameter parsing.
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*
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* The Xtensa port uses a list of variable-sized tags to pass data to
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* the kernel. The first tag must be a BP_TAG_FIRST tag for the list
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* to be recognised. The list is terminated with a zero-sized
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* BP_TAG_LAST tag.
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*/
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typedef struct tagtable {
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u32 tag;
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int (*parse)(const bp_tag_t*);
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} tagtable_t;
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#define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
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__attribute__((used, section(".taglist"))) = { tag, fn }
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/* parse current tag */
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static int __init add_sysmem_bank(unsigned long type, unsigned long start,
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unsigned long end)
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{
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if (sysmem.nr_banks >= SYSMEM_BANKS_MAX) {
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printk(KERN_WARNING
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"Ignoring memory bank 0x%08lx size %ldKB\n",
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start, end - start);
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return -EINVAL;
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}
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sysmem.bank[sysmem.nr_banks].type = type;
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sysmem.bank[sysmem.nr_banks].start = PAGE_ALIGN(start);
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sysmem.bank[sysmem.nr_banks].end = end & PAGE_MASK;
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sysmem.nr_banks++;
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return 0;
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}
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static int __init parse_tag_mem(const bp_tag_t *tag)
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{
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meminfo_t *mi = (meminfo_t *)(tag->data);
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if (mi->type != MEMORY_TYPE_CONVENTIONAL)
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return -1;
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return add_sysmem_bank(mi->type, mi->start, mi->end);
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}
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__tagtable(BP_TAG_MEMORY, parse_tag_mem);
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#ifdef CONFIG_BLK_DEV_INITRD
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static int __init parse_tag_initrd(const bp_tag_t* tag)
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{
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meminfo_t* mi;
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mi = (meminfo_t*)(tag->data);
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initrd_start = (void*)(mi->start);
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initrd_end = (void*)(mi->end);
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return 0;
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}
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__tagtable(BP_TAG_INITRD, parse_tag_initrd);
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#ifdef CONFIG_OF
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static int __init parse_tag_fdt(const bp_tag_t *tag)
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{
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dtb_start = (void *)(tag->data[0]);
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return 0;
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}
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__tagtable(BP_TAG_FDT, parse_tag_fdt);
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void __init early_init_dt_setup_initrd_arch(unsigned long start,
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unsigned long end)
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{
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initrd_start = (void *)__va(start);
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initrd_end = (void *)__va(end);
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initrd_below_start_ok = 1;
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}
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#endif /* CONFIG_OF */
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#endif /* CONFIG_BLK_DEV_INITRD */
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static int __init parse_tag_cmdline(const bp_tag_t* tag)
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{
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strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
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return 0;
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}
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__tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
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static int __init parse_bootparam(const bp_tag_t* tag)
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{
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extern tagtable_t __tagtable_begin, __tagtable_end;
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tagtable_t *t;
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/* Boot parameters must start with a BP_TAG_FIRST tag. */
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if (tag->id != BP_TAG_FIRST) {
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printk(KERN_WARNING "Invalid boot parameters!\n");
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return 0;
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}
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tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
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/* Parse all tags. */
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while (tag != NULL && tag->id != BP_TAG_LAST) {
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for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
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if (tag->id == t->tag) {
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t->parse(tag);
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break;
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}
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}
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if (t == &__tagtable_end)
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printk(KERN_WARNING "Ignoring tag "
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"0x%08x\n", tag->id);
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tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
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}
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return 0;
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}
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#ifdef CONFIG_OF
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void __init early_init_dt_add_memory_arch(u64 base, u64 size)
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{
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size &= PAGE_MASK;
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add_sysmem_bank(MEMORY_TYPE_CONVENTIONAL, base, base + size);
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}
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void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
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{
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return __alloc_bootmem(size, align, 0);
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}
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void __init early_init_devtree(void *params)
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{
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/* Setup flat device-tree pointer */
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initial_boot_params = params;
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/* Retrieve various informations from the /chosen node of the
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* device-tree, including the platform type, initrd location and
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* size, TCE reserve, and more ...
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*/
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if (!command_line[0])
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of_scan_flat_dt(early_init_dt_scan_chosen, command_line);
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/* Scan memory nodes and rebuild MEMBLOCKs */
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of_scan_flat_dt(early_init_dt_scan_root, NULL);
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if (sysmem.nr_banks == 0)
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of_scan_flat_dt(early_init_dt_scan_memory, NULL);
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}
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static void __init copy_devtree(void)
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{
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void *alloc = early_init_dt_alloc_memory_arch(
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be32_to_cpu(initial_boot_params->totalsize), 0);
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if (alloc) {
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memcpy(alloc, initial_boot_params,
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be32_to_cpu(initial_boot_params->totalsize));
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initial_boot_params = alloc;
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}
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}
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static int __init xtensa_device_probe(void)
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{
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of_platform_populate(NULL, NULL, NULL, NULL);
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return 0;
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}
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device_initcall(xtensa_device_probe);
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#endif /* CONFIG_OF */
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/*
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* Initialize architecture. (Early stage)
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*/
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void __init init_arch(bp_tag_t *bp_start)
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{
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sysmem.nr_banks = 0;
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/* Parse boot parameters */
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if (bp_start)
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parse_bootparam(bp_start);
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#ifdef CONFIG_OF
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early_init_devtree(dtb_start);
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#endif
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if (sysmem.nr_banks == 0) {
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sysmem.nr_banks = 1;
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sysmem.bank[0].start = PLATFORM_DEFAULT_MEM_START;
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sysmem.bank[0].end = PLATFORM_DEFAULT_MEM_START
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+ PLATFORM_DEFAULT_MEM_SIZE;
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}
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#ifdef CONFIG_CMDLINE_BOOL
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if (!command_line[0])
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strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
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#endif
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/* Early hook for platforms */
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platform_init(bp_start);
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/* Initialize MMU. */
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init_mmu();
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}
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/*
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* Initialize system. Setup memory and reserve regions.
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*/
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extern char _end;
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extern char _stext;
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extern char _WindowVectors_text_start;
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extern char _WindowVectors_text_end;
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extern char _DebugInterruptVector_literal_start;
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extern char _DebugInterruptVector_text_end;
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extern char _KernelExceptionVector_literal_start;
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extern char _KernelExceptionVector_text_end;
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extern char _UserExceptionVector_literal_start;
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extern char _UserExceptionVector_text_end;
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extern char _DoubleExceptionVector_literal_start;
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extern char _DoubleExceptionVector_text_end;
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#if XCHAL_EXCM_LEVEL >= 2
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extern char _Level2InterruptVector_text_start;
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extern char _Level2InterruptVector_text_end;
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#endif
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#if XCHAL_EXCM_LEVEL >= 3
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extern char _Level3InterruptVector_text_start;
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extern char _Level3InterruptVector_text_end;
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#endif
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#if XCHAL_EXCM_LEVEL >= 4
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extern char _Level4InterruptVector_text_start;
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extern char _Level4InterruptVector_text_end;
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#endif
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#if XCHAL_EXCM_LEVEL >= 5
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extern char _Level5InterruptVector_text_start;
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extern char _Level5InterruptVector_text_end;
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#endif
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#if XCHAL_EXCM_LEVEL >= 6
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extern char _Level6InterruptVector_text_start;
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extern char _Level6InterruptVector_text_end;
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#endif
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#ifdef CONFIG_S32C1I_SELFTEST
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#if XCHAL_HAVE_S32C1I
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static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
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/*
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* Basic atomic compare-and-swap, that records PC of S32C1I for probing.
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*
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* If *v == cmp, set *v = set. Return previous *v.
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*/
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static inline int probed_compare_swap(int *v, int cmp, int set)
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{
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int tmp;
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__asm__ __volatile__(
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" movi %1, 1f\n"
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" s32i %1, %4, 0\n"
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" wsr %2, scompare1\n"
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"1: s32c1i %0, %3, 0\n"
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: "=a" (set), "=&a" (tmp)
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: "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
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: "memory"
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);
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return set;
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}
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/* Handle probed exception */
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void __init do_probed_exception(struct pt_regs *regs, unsigned long exccause)
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{
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if (regs->pc == rcw_probe_pc) { /* exception on s32c1i ? */
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regs->pc += 3; /* skip the s32c1i instruction */
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rcw_exc = exccause;
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} else {
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do_unhandled(regs, exccause);
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}
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}
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/* Simple test of S32C1I (soc bringup assist) */
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void __init check_s32c1i(void)
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{
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int n, cause1, cause2;
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void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
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rcw_probe_pc = 0;
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handbus = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
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do_probed_exception);
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handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
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do_probed_exception);
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handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
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do_probed_exception);
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/* First try an S32C1I that does not store: */
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rcw_exc = 0;
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rcw_word = 1;
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n = probed_compare_swap(&rcw_word, 0, 2);
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cause1 = rcw_exc;
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/* took exception? */
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if (cause1 != 0) {
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/* unclean exception? */
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if (n != 2 || rcw_word != 1)
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panic("S32C1I exception error");
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} else if (rcw_word != 1 || n != 1) {
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panic("S32C1I compare error");
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}
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/* Then an S32C1I that stores: */
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rcw_exc = 0;
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rcw_word = 0x1234567;
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n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
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cause2 = rcw_exc;
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if (cause2 != 0) {
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/* unclean exception? */
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if (n != 0xabcde || rcw_word != 0x1234567)
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panic("S32C1I exception error (b)");
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} else if (rcw_word != 0xabcde || n != 0x1234567) {
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panic("S32C1I store error");
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}
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/* Verify consistency of exceptions: */
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if (cause1 || cause2) {
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pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
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/* If emulation of S32C1I upon bus error gets implemented,
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we can get rid of this panic for single core (not SMP) */
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panic("S32C1I exceptions not currently supported");
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}
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if (cause1 != cause2)
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panic("inconsistent S32C1I exceptions");
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trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
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trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
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trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
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}
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#else /* XCHAL_HAVE_S32C1I */
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/* This condition should not occur with a commercially deployed processor.
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Display reminder for early engr test or demo chips / FPGA bitstreams */
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void __init check_s32c1i(void)
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{
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pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
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}
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#endif /* XCHAL_HAVE_S32C1I */
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#else /* CONFIG_S32C1I_SELFTEST */
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void __init check_s32c1i(void)
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{
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}
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#endif /* CONFIG_S32C1I_SELFTEST */
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void __init setup_arch(char **cmdline_p)
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{
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strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
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*cmdline_p = command_line;
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check_s32c1i();
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/* Reserve some memory regions */
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start < initrd_end) {
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initrd_is_mapped = mem_reserve(__pa(initrd_start),
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__pa(initrd_end), 0);
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initrd_below_start_ok = 1;
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} else {
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initrd_start = 0;
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}
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#endif
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mem_reserve(__pa(&_stext),__pa(&_end), 1);
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mem_reserve(__pa(&_WindowVectors_text_start),
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__pa(&_WindowVectors_text_end), 0);
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mem_reserve(__pa(&_DebugInterruptVector_literal_start),
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__pa(&_DebugInterruptVector_text_end), 0);
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mem_reserve(__pa(&_KernelExceptionVector_literal_start),
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__pa(&_KernelExceptionVector_text_end), 0);
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mem_reserve(__pa(&_UserExceptionVector_literal_start),
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__pa(&_UserExceptionVector_text_end), 0);
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mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
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__pa(&_DoubleExceptionVector_text_end), 0);
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#if XCHAL_EXCM_LEVEL >= 2
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mem_reserve(__pa(&_Level2InterruptVector_text_start),
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__pa(&_Level2InterruptVector_text_end), 0);
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#endif
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#if XCHAL_EXCM_LEVEL >= 3
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mem_reserve(__pa(&_Level3InterruptVector_text_start),
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__pa(&_Level3InterruptVector_text_end), 0);
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#endif
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#if XCHAL_EXCM_LEVEL >= 4
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mem_reserve(__pa(&_Level4InterruptVector_text_start),
|
|
__pa(&_Level4InterruptVector_text_end), 0);
|
|
#endif
|
|
#if XCHAL_EXCM_LEVEL >= 5
|
|
mem_reserve(__pa(&_Level5InterruptVector_text_start),
|
|
__pa(&_Level5InterruptVector_text_end), 0);
|
|
#endif
|
|
#if XCHAL_EXCM_LEVEL >= 6
|
|
mem_reserve(__pa(&_Level6InterruptVector_text_start),
|
|
__pa(&_Level6InterruptVector_text_end), 0);
|
|
#endif
|
|
|
|
bootmem_init();
|
|
|
|
#ifdef CONFIG_OF
|
|
copy_devtree();
|
|
unflatten_device_tree();
|
|
#endif
|
|
|
|
platform_setup(cmdline_p);
|
|
|
|
paging_init();
|
|
zones_init();
|
|
|
|
#ifdef CONFIG_VT
|
|
# if defined(CONFIG_VGA_CONSOLE)
|
|
conswitchp = &vga_con;
|
|
# elif defined(CONFIG_DUMMY_CONSOLE)
|
|
conswitchp = &dummy_con;
|
|
# endif
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCI
|
|
platform_pcibios_init();
|
|
#endif
|
|
}
|
|
|
|
void machine_restart(char * cmd)
|
|
{
|
|
platform_restart();
|
|
}
|
|
|
|
void machine_halt(void)
|
|
{
|
|
platform_halt();
|
|
while (1);
|
|
}
|
|
|
|
void machine_power_off(void)
|
|
{
|
|
platform_power_off();
|
|
while (1);
|
|
}
|
|
#ifdef CONFIG_PROC_FS
|
|
|
|
/*
|
|
* Display some core information through /proc/cpuinfo.
|
|
*/
|
|
|
|
static int
|
|
c_show(struct seq_file *f, void *slot)
|
|
{
|
|
/* high-level stuff */
|
|
seq_printf(f,"processor\t: 0\n"
|
|
"vendor_id\t: Tensilica\n"
|
|
"model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
|
|
"core ID\t\t: " XCHAL_CORE_ID "\n"
|
|
"build ID\t: 0x%x\n"
|
|
"byte order\t: %s\n"
|
|
"cpu MHz\t\t: %lu.%02lu\n"
|
|
"bogomips\t: %lu.%02lu\n",
|
|
XCHAL_BUILD_UNIQUE_ID,
|
|
XCHAL_HAVE_BE ? "big" : "little",
|
|
CCOUNT_PER_JIFFY/(1000000/HZ),
|
|
(CCOUNT_PER_JIFFY/(10000/HZ)) % 100,
|
|
loops_per_jiffy/(500000/HZ),
|
|
(loops_per_jiffy/(5000/HZ)) % 100);
|
|
|
|
seq_printf(f,"flags\t\t: "
|
|
#if XCHAL_HAVE_NMI
|
|
"nmi "
|
|
#endif
|
|
#if XCHAL_HAVE_DEBUG
|
|
"debug "
|
|
# if XCHAL_HAVE_OCD
|
|
"ocd "
|
|
# endif
|
|
#endif
|
|
#if XCHAL_HAVE_DENSITY
|
|
"density "
|
|
#endif
|
|
#if XCHAL_HAVE_BOOLEANS
|
|
"boolean "
|
|
#endif
|
|
#if XCHAL_HAVE_LOOPS
|
|
"loop "
|
|
#endif
|
|
#if XCHAL_HAVE_NSA
|
|
"nsa "
|
|
#endif
|
|
#if XCHAL_HAVE_MINMAX
|
|
"minmax "
|
|
#endif
|
|
#if XCHAL_HAVE_SEXT
|
|
"sext "
|
|
#endif
|
|
#if XCHAL_HAVE_CLAMPS
|
|
"clamps "
|
|
#endif
|
|
#if XCHAL_HAVE_MAC16
|
|
"mac16 "
|
|
#endif
|
|
#if XCHAL_HAVE_MUL16
|
|
"mul16 "
|
|
#endif
|
|
#if XCHAL_HAVE_MUL32
|
|
"mul32 "
|
|
#endif
|
|
#if XCHAL_HAVE_MUL32_HIGH
|
|
"mul32h "
|
|
#endif
|
|
#if XCHAL_HAVE_FP
|
|
"fpu "
|
|
#endif
|
|
#if XCHAL_HAVE_S32C1I
|
|
"s32c1i "
|
|
#endif
|
|
"\n");
|
|
|
|
/* Registers. */
|
|
seq_printf(f,"physical aregs\t: %d\n"
|
|
"misc regs\t: %d\n"
|
|
"ibreak\t\t: %d\n"
|
|
"dbreak\t\t: %d\n",
|
|
XCHAL_NUM_AREGS,
|
|
XCHAL_NUM_MISC_REGS,
|
|
XCHAL_NUM_IBREAK,
|
|
XCHAL_NUM_DBREAK);
|
|
|
|
|
|
/* Interrupt. */
|
|
seq_printf(f,"num ints\t: %d\n"
|
|
"ext ints\t: %d\n"
|
|
"int levels\t: %d\n"
|
|
"timers\t\t: %d\n"
|
|
"debug level\t: %d\n",
|
|
XCHAL_NUM_INTERRUPTS,
|
|
XCHAL_NUM_EXTINTERRUPTS,
|
|
XCHAL_NUM_INTLEVELS,
|
|
XCHAL_NUM_TIMERS,
|
|
XCHAL_DEBUGLEVEL);
|
|
|
|
/* Cache */
|
|
seq_printf(f,"icache line size: %d\n"
|
|
"icache ways\t: %d\n"
|
|
"icache size\t: %d\n"
|
|
"icache flags\t: "
|
|
#if XCHAL_ICACHE_LINE_LOCKABLE
|
|
"lock "
|
|
#endif
|
|
"\n"
|
|
"dcache line size: %d\n"
|
|
"dcache ways\t: %d\n"
|
|
"dcache size\t: %d\n"
|
|
"dcache flags\t: "
|
|
#if XCHAL_DCACHE_IS_WRITEBACK
|
|
"writeback "
|
|
#endif
|
|
#if XCHAL_DCACHE_LINE_LOCKABLE
|
|
"lock "
|
|
#endif
|
|
"\n",
|
|
XCHAL_ICACHE_LINESIZE,
|
|
XCHAL_ICACHE_WAYS,
|
|
XCHAL_ICACHE_SIZE,
|
|
XCHAL_DCACHE_LINESIZE,
|
|
XCHAL_DCACHE_WAYS,
|
|
XCHAL_DCACHE_SIZE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* We show only CPU #0 info.
|
|
*/
|
|
static void *
|
|
c_start(struct seq_file *f, loff_t *pos)
|
|
{
|
|
return (void *) ((*pos == 0) ? (void *)1 : NULL);
|
|
}
|
|
|
|
static void *
|
|
c_next(struct seq_file *f, void *v, loff_t *pos)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
static void
|
|
c_stop(struct seq_file *f, void *v)
|
|
{
|
|
}
|
|
|
|
const struct seq_operations cpuinfo_op =
|
|
{
|
|
start: c_start,
|
|
next: c_next,
|
|
stop: c_stop,
|
|
show: c_show
|
|
};
|
|
|
|
#endif /* CONFIG_PROC_FS */
|