1076 lines
25 KiB
C
1076 lines
25 KiB
C
/* bnx2x_cmn.h: Broadcom Everest network driver.
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*
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* Copyright (c) 2007-2010 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation.
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*
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* Maintained by: Eilon Greenstein <eilong@broadcom.com>
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* Written by: Eliezer Tamir
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* Based on code from Michael Chan's bnx2 driver
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* UDP CSUM errata workaround by Arik Gendelman
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* Slowpath and fastpath rework by Vladislav Zolotarov
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* Statistics and Link management by Yitchak Gertner
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*
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*/
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#ifndef BNX2X_CMN_H
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#define BNX2X_CMN_H
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#include <linux/types.h>
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#include <linux/netdevice.h>
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#include "bnx2x.h"
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extern int num_queues;
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/*********************** Interfaces ****************************
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* Functions that need to be implemented by each driver version
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*/
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/**
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* Initialize link parameters structure variables.
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*
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* @param bp
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* @param load_mode
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*
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* @return u8
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*/
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u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
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/**
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* Configure hw according to link parameters structure.
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*
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* @param bp
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*/
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void bnx2x_link_set(struct bnx2x *bp);
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/**
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* Query link status
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*
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* @param bp
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* @param is_serdes
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*
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* @return 0 - link is UP
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*/
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u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
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/**
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* Handles link status change
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*
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* @param bp
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*/
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void bnx2x__link_status_update(struct bnx2x *bp);
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/**
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* Report link status to upper layer
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*
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* @param bp
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*
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* @return int
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*/
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void bnx2x_link_report(struct bnx2x *bp);
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/**
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* calculates MF speed according to current linespeed and MF
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* configuration
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*
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* @param bp
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*
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* @return u16
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*/
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u16 bnx2x_get_mf_speed(struct bnx2x *bp);
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/**
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* MSI-X slowpath interrupt handler
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*
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* @param irq
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* @param dev_instance
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*
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* @return irqreturn_t
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*/
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irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
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/**
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* non MSI-X interrupt handler
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*
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* @param irq
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* @param dev_instance
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*
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* @return irqreturn_t
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*/
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irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
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#ifdef BCM_CNIC
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/**
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* Send command to cnic driver
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*
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* @param bp
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* @param cmd
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*/
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int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
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/**
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* Provides cnic information for proper interrupt handling
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*
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* @param bp
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*/
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void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
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#endif
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/**
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* Enable HW interrupts.
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*
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* @param bp
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*/
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void bnx2x_int_enable(struct bnx2x *bp);
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/**
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* Disable interrupts. This function ensures that there are no
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* ISRs or SP DPCs (sp_task) are running after it returns.
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*
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* @param bp
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* @param disable_hw if true, disable HW interrupts.
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*/
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void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
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/**
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* Loads device firmware
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*
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* @param bp
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*
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* @return int
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*/
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int bnx2x_init_firmware(struct bnx2x *bp);
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/**
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* Init HW blocks according to current initialization stage:
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* COMMON, PORT or FUNCTION.
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*
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* @param bp
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* @param load_code: COMMON, PORT or FUNCTION
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*
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* @return int
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*/
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int bnx2x_init_hw(struct bnx2x *bp, u32 load_code);
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/**
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* Init driver internals:
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* - rings
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* - status blocks
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* - etc.
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*
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* @param bp
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* @param load_code COMMON, PORT or FUNCTION
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*/
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void bnx2x_nic_init(struct bnx2x *bp, u32 load_code);
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/**
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* Allocate driver's memory.
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*
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* @param bp
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*
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* @return int
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*/
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int bnx2x_alloc_mem(struct bnx2x *bp);
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/**
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* Release driver's memory.
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*
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* @param bp
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*/
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void bnx2x_free_mem(struct bnx2x *bp);
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/**
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* Setup eth Client.
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*
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* @param bp
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* @param fp
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* @param is_leading
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*
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* @return int
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*/
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int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
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int is_leading);
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/**
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* Set number of queues according to mode
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*
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* @param bp
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*
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*/
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void bnx2x_set_num_queues(struct bnx2x *bp);
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/**
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* Cleanup chip internals:
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* - Cleanup MAC configuration.
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* - Close clients.
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* - etc.
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*
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* @param bp
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* @param unload_mode
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*/
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void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode);
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/**
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* Acquire HW lock.
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*
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* @param bp
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* @param resource Resource bit which was locked
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*
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* @return int
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*/
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int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
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/**
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* Release HW lock.
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*
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* @param bp driver handle
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* @param resource Resource bit which was locked
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*
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* @return int
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*/
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int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
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/**
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* Configure eth MAC address in the HW according to the value in
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* netdev->dev_addr.
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*
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* @param bp driver handle
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* @param set
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*/
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void bnx2x_set_eth_mac(struct bnx2x *bp, int set);
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#ifdef BCM_CNIC
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/**
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* Set/Clear FIP MAC(s) at the next enties in the CAM after the ETH
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* MAC(s). This function will wait until the ramdord completion
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* returns.
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*
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* @param bp driver handle
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* @param set set or clear the CAM entry
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*
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* @return 0 if cussess, -ENODEV if ramrod doesn't return.
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*/
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int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set);
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/**
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* Set/Clear ALL_ENODE mcast MAC.
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*
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* @param bp
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* @param set
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*
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* @return int
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*/
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int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set);
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#endif
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/**
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* Set MAC filtering configurations.
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*
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* @remarks called with netif_tx_lock from dev_mcast.c
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*
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* @param dev net_device
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*/
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void bnx2x_set_rx_mode(struct net_device *dev);
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/**
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* Configure MAC filtering rules in a FW.
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*
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* @param bp driver handle
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*/
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void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
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/* Parity errors related */
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void bnx2x_inc_load_cnt(struct bnx2x *bp);
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u32 bnx2x_dec_load_cnt(struct bnx2x *bp);
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bool bnx2x_chk_parity_attn(struct bnx2x *bp);
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bool bnx2x_reset_is_done(struct bnx2x *bp);
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void bnx2x_disable_close_the_gate(struct bnx2x *bp);
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/**
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* Perform statistics handling according to event
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*
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* @param bp driver handle
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* @param event bnx2x_stats_event
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*/
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void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
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/**
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* Handle ramrods completion
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*
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* @param fp fastpath handle for the event
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* @param rr_cqe eth_rx_cqe
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*/
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void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
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/**
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* Init/halt function before/after sending
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* CLIENT_SETUP/CFC_DEL for the first/last client.
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*
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* @param bp
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*
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* @return int
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*/
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int bnx2x_func_start(struct bnx2x *bp);
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/**
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* Prepare ILT configurations according to current driver
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* parameters.
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*
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* @param bp
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*/
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void bnx2x_ilt_set_info(struct bnx2x *bp);
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/**
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* Inintialize dcbx protocol
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*
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* @param bp
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*/
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void bnx2x_dcbx_init(struct bnx2x *bp);
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/**
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* Set power state to the requested value. Currently only D0 and
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* D3hot are supported.
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*
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* @param bp
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* @param state D0 or D3hot
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*
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* @return int
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*/
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int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
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/**
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* Updates MAX part of MF configuration in HW
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* (if required)
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*
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* @param bp
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* @param value
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*/
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void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value);
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/* dev_close main block */
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int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode);
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/* dev_open main block */
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int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
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/* hard_xmit callback */
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netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
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/* select_queue callback */
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u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb);
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int bnx2x_change_mac_addr(struct net_device *dev, void *p);
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/* NAPI poll Rx part */
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int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget);
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/* NAPI poll Tx part */
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int bnx2x_tx_int(struct bnx2x_fastpath *fp);
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/* suspend/resume callbacks */
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int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
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int bnx2x_resume(struct pci_dev *pdev);
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/* Release IRQ vectors */
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void bnx2x_free_irq(struct bnx2x *bp);
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void bnx2x_init_rx_rings(struct bnx2x *bp);
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void bnx2x_free_skbs(struct bnx2x *bp);
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void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
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void bnx2x_netif_start(struct bnx2x *bp);
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/**
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* Fill msix_table, request vectors, update num_queues according
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* to number of available vectors
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*
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* @param bp
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*
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* @return int
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*/
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int bnx2x_enable_msix(struct bnx2x *bp);
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/**
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* Request msi mode from OS, updated internals accordingly
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*
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* @param bp
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*
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* @return int
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*/
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int bnx2x_enable_msi(struct bnx2x *bp);
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/**
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* NAPI callback
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*
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* @param napi
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* @param budget
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*
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* @return int
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*/
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int bnx2x_poll(struct napi_struct *napi, int budget);
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/**
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* Allocate/release memories outsize main driver structure
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*
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* @param bp
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*
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* @return int
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*/
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int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp);
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void bnx2x_free_mem_bp(struct bnx2x *bp);
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/**
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* Change mtu netdev callback
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*
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* @param dev
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* @param new_mtu
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*
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* @return int
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*/
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int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
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/**
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* tx timeout netdev callback
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*
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* @param dev
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* @param new_mtu
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*
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* @return int
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*/
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void bnx2x_tx_timeout(struct net_device *dev);
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#ifdef BCM_VLAN
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/**
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* vlan rx register netdev callback
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*
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* @param dev
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* @param new_mtu
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*
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* @return int
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*/
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void bnx2x_vlan_rx_register(struct net_device *dev,
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struct vlan_group *vlgrp);
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#endif
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static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
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{
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barrier(); /* status block is written to by the chip */
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fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
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}
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static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
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struct bnx2x_fastpath *fp,
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u16 bd_prod, u16 rx_comp_prod,
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u16 rx_sge_prod)
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{
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struct ustorm_eth_rx_producers rx_prods = {0};
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int i;
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/* Update producers */
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rx_prods.bd_prod = bd_prod;
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rx_prods.cqe_prod = rx_comp_prod;
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rx_prods.sge_prod = rx_sge_prod;
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/*
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* Make sure that the BD and SGE data is updated before updating the
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* producers since FW might read the BD/SGE right after the producer
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* is updated.
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* This is only applicable for weak-ordered memory model archs such
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* as IA-64. The following barrier is also mandatory since FW will
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* assumes BDs must have buffers.
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*/
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wmb();
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for (i = 0; i < sizeof(struct ustorm_eth_rx_producers)/4; i++)
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REG_WR(bp,
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BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset + i*4,
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((u32 *)&rx_prods)[i]);
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mmiowb(); /* keep prod updates ordered */
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DP(NETIF_MSG_RX_STATUS,
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"queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
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fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
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}
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static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
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u8 segment, u16 index, u8 op,
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u8 update, u32 igu_addr)
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{
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struct igu_regular cmd_data = {0};
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cmd_data.sb_id_and_flags =
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((index << IGU_REGULAR_SB_INDEX_SHIFT) |
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(segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
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(update << IGU_REGULAR_BUPDATE_SHIFT) |
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(op << IGU_REGULAR_ENABLE_INT_SHIFT));
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DP(NETIF_MSG_HW, "write 0x%08x to IGU addr 0x%x\n",
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cmd_data.sb_id_and_flags, igu_addr);
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REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
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/* Make sure that ACK is written */
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mmiowb();
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barrier();
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}
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static inline void bnx2x_igu_clear_sb_gen(struct bnx2x *bp,
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u8 idu_sb_id, bool is_Pf)
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{
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u32 data, ctl, cnt = 100;
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u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
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u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
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u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
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u32 sb_bit = 1 << (idu_sb_id%32);
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u32 func_encode = BP_FUNC(bp) |
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((is_Pf == true ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT);
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u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
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/* Not supported in BC mode */
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if (CHIP_INT_MODE_IS_BC(bp))
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return;
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data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
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<< IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
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IGU_REGULAR_CLEANUP_SET |
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IGU_REGULAR_BCLEANUP;
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ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
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func_encode << IGU_CTRL_REG_FID_SHIFT |
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IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
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DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
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data, igu_addr_data);
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REG_WR(bp, igu_addr_data, data);
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mmiowb();
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barrier();
|
|
DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
|
|
ctl, igu_addr_ctl);
|
|
REG_WR(bp, igu_addr_ctl, ctl);
|
|
mmiowb();
|
|
barrier();
|
|
|
|
/* wait for clean up to finish */
|
|
while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
|
|
msleep(20);
|
|
|
|
|
|
if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
|
|
DP(NETIF_MSG_HW, "Unable to finish IGU cleanup: "
|
|
"idu_sb_id %d offset %d bit %d (cnt %d)\n",
|
|
idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
|
|
}
|
|
}
|
|
|
|
static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
|
|
u8 storm, u16 index, u8 op, u8 update)
|
|
{
|
|
u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
|
|
COMMAND_REG_INT_ACK);
|
|
struct igu_ack_register igu_ack;
|
|
|
|
igu_ack.status_block_index = index;
|
|
igu_ack.sb_id_and_flags =
|
|
((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
|
|
(storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
|
|
(update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
|
|
(op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
|
|
|
|
DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
|
|
(*(u32 *)&igu_ack), hc_addr);
|
|
REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
|
|
|
|
/* Make sure that ACK is written */
|
|
mmiowb();
|
|
barrier();
|
|
}
|
|
|
|
static inline void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
|
|
u16 index, u8 op, u8 update)
|
|
{
|
|
u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
|
|
|
|
bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
|
|
igu_addr);
|
|
}
|
|
|
|
static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
|
|
u16 index, u8 op, u8 update)
|
|
{
|
|
if (bp->common.int_block == INT_BLOCK_HC)
|
|
bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
|
|
else {
|
|
u8 segment;
|
|
|
|
if (CHIP_INT_MODE_IS_BC(bp))
|
|
segment = storm;
|
|
else if (igu_sb_id != bp->igu_dsb_id)
|
|
segment = IGU_SEG_ACCESS_DEF;
|
|
else if (storm == ATTENTION_ID)
|
|
segment = IGU_SEG_ACCESS_ATTN;
|
|
else
|
|
segment = IGU_SEG_ACCESS_DEF;
|
|
bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
|
|
}
|
|
}
|
|
|
|
static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
|
|
{
|
|
u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
|
|
COMMAND_REG_SIMD_MASK);
|
|
u32 result = REG_RD(bp, hc_addr);
|
|
|
|
DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
|
|
result, hc_addr);
|
|
|
|
barrier();
|
|
return result;
|
|
}
|
|
|
|
static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
|
|
{
|
|
u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
|
|
u32 result = REG_RD(bp, igu_addr);
|
|
|
|
DP(NETIF_MSG_HW, "read 0x%08x from IGU addr 0x%x\n",
|
|
result, igu_addr);
|
|
|
|
barrier();
|
|
return result;
|
|
}
|
|
|
|
static inline u16 bnx2x_ack_int(struct bnx2x *bp)
|
|
{
|
|
barrier();
|
|
if (bp->common.int_block == INT_BLOCK_HC)
|
|
return bnx2x_hc_ack_int(bp);
|
|
else
|
|
return bnx2x_igu_ack_int(bp);
|
|
}
|
|
|
|
static inline int bnx2x_has_tx_work_unload(struct bnx2x_fastpath *fp)
|
|
{
|
|
/* Tell compiler that consumer and producer can change */
|
|
barrier();
|
|
return fp->tx_pkt_prod != fp->tx_pkt_cons;
|
|
}
|
|
|
|
static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
|
|
{
|
|
s16 used;
|
|
u16 prod;
|
|
u16 cons;
|
|
|
|
prod = fp->tx_bd_prod;
|
|
cons = fp->tx_bd_cons;
|
|
|
|
/* NUM_TX_RINGS = number of "next-page" entries
|
|
It will be used as a threshold */
|
|
used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
|
|
|
|
#ifdef BNX2X_STOP_ON_ERROR
|
|
WARN_ON(used < 0);
|
|
WARN_ON(used > fp->bp->tx_ring_size);
|
|
WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
|
|
#endif
|
|
|
|
return (s16)(fp->bp->tx_ring_size) - used;
|
|
}
|
|
|
|
static inline int bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
|
|
{
|
|
u16 hw_cons;
|
|
|
|
/* Tell compiler that status block fields can change */
|
|
barrier();
|
|
hw_cons = le16_to_cpu(*fp->tx_cons_sb);
|
|
return hw_cons != fp->tx_pkt_cons;
|
|
}
|
|
|
|
static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
|
|
{
|
|
u16 rx_cons_sb;
|
|
|
|
/* Tell compiler that status block fields can change */
|
|
barrier();
|
|
rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
|
|
if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
|
|
rx_cons_sb++;
|
|
return (fp->rx_comp_cons != rx_cons_sb);
|
|
}
|
|
|
|
/**
|
|
* disables tx from stack point of view
|
|
*
|
|
* @param bp
|
|
*/
|
|
static inline void bnx2x_tx_disable(struct bnx2x *bp)
|
|
{
|
|
netif_tx_disable(bp->dev);
|
|
netif_carrier_off(bp->dev);
|
|
}
|
|
|
|
static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
|
|
struct bnx2x_fastpath *fp, u16 index)
|
|
{
|
|
struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
|
|
struct page *page = sw_buf->page;
|
|
struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
|
|
|
|
/* Skip "next page" elements */
|
|
if (!page)
|
|
return;
|
|
|
|
dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
|
|
SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
|
|
__free_pages(page, PAGES_PER_SGE_SHIFT);
|
|
|
|
sw_buf->page = NULL;
|
|
sge->addr_hi = 0;
|
|
sge->addr_lo = 0;
|
|
}
|
|
|
|
static inline void bnx2x_add_all_napi(struct bnx2x *bp)
|
|
{
|
|
int i;
|
|
|
|
/* Add NAPI objects */
|
|
for_each_napi_queue(bp, i)
|
|
netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
|
|
bnx2x_poll, BNX2X_NAPI_WEIGHT);
|
|
}
|
|
|
|
static inline void bnx2x_del_all_napi(struct bnx2x *bp)
|
|
{
|
|
int i;
|
|
|
|
for_each_napi_queue(bp, i)
|
|
netif_napi_del(&bnx2x_fp(bp, i, napi));
|
|
}
|
|
|
|
static inline void bnx2x_disable_msi(struct bnx2x *bp)
|
|
{
|
|
if (bp->flags & USING_MSIX_FLAG) {
|
|
pci_disable_msix(bp->pdev);
|
|
bp->flags &= ~USING_MSIX_FLAG;
|
|
} else if (bp->flags & USING_MSI_FLAG) {
|
|
pci_disable_msi(bp->pdev);
|
|
bp->flags &= ~USING_MSI_FLAG;
|
|
}
|
|
}
|
|
|
|
static inline int bnx2x_calc_num_queues(struct bnx2x *bp)
|
|
{
|
|
return num_queues ?
|
|
min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) :
|
|
min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp));
|
|
}
|
|
|
|
static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
|
|
{
|
|
int i, j;
|
|
|
|
for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
|
|
int idx = RX_SGE_CNT * i - 1;
|
|
|
|
for (j = 0; j < 2; j++) {
|
|
SGE_MASK_CLEAR_BIT(fp, idx);
|
|
idx--;
|
|
}
|
|
}
|
|
}
|
|
|
|
static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
|
|
{
|
|
/* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
|
|
memset(fp->sge_mask, 0xff,
|
|
(NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
|
|
|
|
/* Clear the two last indices in the page to 1:
|
|
these are the indices that correspond to the "next" element,
|
|
hence will never be indicated and should be removed from
|
|
the calculations. */
|
|
bnx2x_clear_sge_mask_next_elems(fp);
|
|
}
|
|
|
|
static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
|
|
struct bnx2x_fastpath *fp, u16 index)
|
|
{
|
|
struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
|
|
struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
|
|
struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
|
|
dma_addr_t mapping;
|
|
|
|
if (unlikely(page == NULL))
|
|
return -ENOMEM;
|
|
|
|
mapping = dma_map_page(&bp->pdev->dev, page, 0,
|
|
SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
|
|
if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
|
|
__free_pages(page, PAGES_PER_SGE_SHIFT);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
sw_buf->page = page;
|
|
dma_unmap_addr_set(sw_buf, mapping, mapping);
|
|
|
|
sge->addr_hi = cpu_to_le32(U64_HI(mapping));
|
|
sge->addr_lo = cpu_to_le32(U64_LO(mapping));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
|
|
struct bnx2x_fastpath *fp, u16 index)
|
|
{
|
|
struct sk_buff *skb;
|
|
struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
|
|
struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
|
|
dma_addr_t mapping;
|
|
|
|
skb = netdev_alloc_skb(bp->dev, fp->rx_buf_size);
|
|
if (unlikely(skb == NULL))
|
|
return -ENOMEM;
|
|
|
|
mapping = dma_map_single(&bp->pdev->dev, skb->data, fp->rx_buf_size,
|
|
DMA_FROM_DEVICE);
|
|
if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
|
|
dev_kfree_skb(skb);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
rx_buf->skb = skb;
|
|
dma_unmap_addr_set(rx_buf, mapping, mapping);
|
|
|
|
rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
|
|
rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* note that we are not allocating a new skb,
|
|
* we are just moving one from cons to prod
|
|
* we are not creating a new mapping,
|
|
* so there is no need to check for dma_mapping_error().
|
|
*/
|
|
static inline void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
|
|
u16 cons, u16 prod)
|
|
{
|
|
struct bnx2x *bp = fp->bp;
|
|
struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
|
|
struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
|
|
struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
|
|
struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
|
|
|
|
dma_sync_single_for_device(&bp->pdev->dev,
|
|
dma_unmap_addr(cons_rx_buf, mapping),
|
|
RX_COPY_THRESH, DMA_FROM_DEVICE);
|
|
|
|
prod_rx_buf->skb = cons_rx_buf->skb;
|
|
dma_unmap_addr_set(prod_rx_buf, mapping,
|
|
dma_unmap_addr(cons_rx_buf, mapping));
|
|
*prod_bd = *cons_bd;
|
|
}
|
|
|
|
static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
|
|
struct bnx2x_fastpath *fp, int last)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < last; i++)
|
|
bnx2x_free_rx_sge(bp, fp, i);
|
|
}
|
|
|
|
static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
|
|
struct bnx2x_fastpath *fp, int last)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < last; i++) {
|
|
struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
|
|
struct sk_buff *skb = rx_buf->skb;
|
|
|
|
if (skb == NULL) {
|
|
DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
|
|
continue;
|
|
}
|
|
|
|
if (fp->tpa_state[i] == BNX2X_TPA_START)
|
|
dma_unmap_single(&bp->pdev->dev,
|
|
dma_unmap_addr(rx_buf, mapping),
|
|
fp->rx_buf_size, DMA_FROM_DEVICE);
|
|
|
|
dev_kfree_skb(skb);
|
|
rx_buf->skb = NULL;
|
|
}
|
|
}
|
|
|
|
|
|
static inline void bnx2x_init_tx_rings(struct bnx2x *bp)
|
|
{
|
|
int i, j;
|
|
|
|
for_each_tx_queue(bp, j) {
|
|
struct bnx2x_fastpath *fp = &bp->fp[j];
|
|
|
|
for (i = 1; i <= NUM_TX_RINGS; i++) {
|
|
struct eth_tx_next_bd *tx_next_bd =
|
|
&fp->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
|
|
|
|
tx_next_bd->addr_hi =
|
|
cpu_to_le32(U64_HI(fp->tx_desc_mapping +
|
|
BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
|
|
tx_next_bd->addr_lo =
|
|
cpu_to_le32(U64_LO(fp->tx_desc_mapping +
|
|
BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
|
|
}
|
|
|
|
SET_FLAG(fp->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
|
|
fp->tx_db.data.zero_fill1 = 0;
|
|
fp->tx_db.data.prod = 0;
|
|
|
|
fp->tx_pkt_prod = 0;
|
|
fp->tx_pkt_cons = 0;
|
|
fp->tx_bd_prod = 0;
|
|
fp->tx_bd_cons = 0;
|
|
fp->tx_pkt = 0;
|
|
}
|
|
}
|
|
|
|
static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
|
|
{
|
|
int i;
|
|
|
|
for (i = 1; i <= NUM_RX_RINGS; i++) {
|
|
struct eth_rx_bd *rx_bd;
|
|
|
|
rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
|
|
rx_bd->addr_hi =
|
|
cpu_to_le32(U64_HI(fp->rx_desc_mapping +
|
|
BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
|
|
rx_bd->addr_lo =
|
|
cpu_to_le32(U64_LO(fp->rx_desc_mapping +
|
|
BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
|
|
}
|
|
}
|
|
|
|
static inline void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
|
|
{
|
|
int i;
|
|
|
|
for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
|
|
struct eth_rx_sge *sge;
|
|
|
|
sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
|
|
sge->addr_hi =
|
|
cpu_to_le32(U64_HI(fp->rx_sge_mapping +
|
|
BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
|
|
|
|
sge->addr_lo =
|
|
cpu_to_le32(U64_LO(fp->rx_sge_mapping +
|
|
BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
|
|
}
|
|
}
|
|
|
|
static inline void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp)
|
|
{
|
|
int i;
|
|
for (i = 1; i <= NUM_RCQ_RINGS; i++) {
|
|
struct eth_rx_cqe_next_page *nextpg;
|
|
|
|
nextpg = (struct eth_rx_cqe_next_page *)
|
|
&fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
|
|
nextpg->addr_hi =
|
|
cpu_to_le32(U64_HI(fp->rx_comp_mapping +
|
|
BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
|
|
nextpg->addr_lo =
|
|
cpu_to_le32(U64_LO(fp->rx_comp_mapping +
|
|
BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
|
|
}
|
|
}
|
|
|
|
#ifdef BCM_CNIC
|
|
static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp)
|
|
{
|
|
bnx2x_fcoe(bp, cl_id) = BNX2X_FCOE_ETH_CL_ID +
|
|
BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
|
|
bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID;
|
|
bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
|
|
bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
|
|
bnx2x_fcoe(bp, bp) = bp;
|
|
bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
|
|
bnx2x_fcoe(bp, index) = FCOE_IDX;
|
|
bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
|
|
bnx2x_fcoe(bp, tx_cons_sb) = BNX2X_FCOE_L2_TX_INDEX;
|
|
/* qZone id equals to FW (per path) client id */
|
|
bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fcoe(bp, cl_id) +
|
|
BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
|
|
ETH_MAX_RX_CLIENTS_E1H);
|
|
/* init shortcut */
|
|
bnx2x_fcoe(bp, ustorm_rx_prods_offset) = CHIP_IS_E2(bp) ?
|
|
USTORM_RX_PRODS_E2_OFFSET(bnx2x_fcoe(bp, cl_qzone_id)) :
|
|
USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), bnx2x_fcoe_fp(bp)->cl_id);
|
|
|
|
}
|
|
#endif
|
|
|
|
static inline void __storm_memset_struct(struct bnx2x *bp,
|
|
u32 addr, size_t size, u32 *data)
|
|
{
|
|
int i;
|
|
for (i = 0; i < size/4; i++)
|
|
REG_WR(bp, addr + (i * 4), data[i]);
|
|
}
|
|
|
|
static inline void storm_memset_mac_filters(struct bnx2x *bp,
|
|
struct tstorm_eth_mac_filter_config *mac_filters,
|
|
u16 abs_fid)
|
|
{
|
|
size_t size = sizeof(struct tstorm_eth_mac_filter_config);
|
|
|
|
u32 addr = BAR_TSTRORM_INTMEM +
|
|
TSTORM_MAC_FILTER_CONFIG_OFFSET(abs_fid);
|
|
|
|
__storm_memset_struct(bp, addr, size, (u32 *)mac_filters);
|
|
}
|
|
|
|
static inline void storm_memset_cmng(struct bnx2x *bp,
|
|
struct cmng_struct_per_port *cmng,
|
|
u8 port)
|
|
{
|
|
size_t size = sizeof(struct cmng_struct_per_port);
|
|
|
|
u32 addr = BAR_XSTRORM_INTMEM +
|
|
XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
|
|
|
|
__storm_memset_struct(bp, addr, size, (u32 *)cmng);
|
|
}
|
|
|
|
/* HW Lock for shared dual port PHYs */
|
|
void bnx2x_acquire_phy_lock(struct bnx2x *bp);
|
|
void bnx2x_release_phy_lock(struct bnx2x *bp);
|
|
|
|
/**
|
|
* Extracts MAX BW part from MF configuration.
|
|
*
|
|
* @param bp
|
|
* @param mf_cfg
|
|
*
|
|
* @return u16
|
|
*/
|
|
static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg)
|
|
{
|
|
u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
|
|
FUNC_MF_CFG_MAX_BW_SHIFT;
|
|
if (!max_cfg) {
|
|
BNX2X_ERR("Illegal configuration detected for Max BW - "
|
|
"using 100 instead\n");
|
|
max_cfg = 100;
|
|
}
|
|
return max_cfg;
|
|
}
|
|
|
|
#endif /* BNX2X_CMN_H */
|