0ecdca26e5
This results in smaller/faster/simpler code and allows future optimizations.
Also remove no longer needed ide[_mm]_{inl,outl}() and ide_hwif_t.{INL,OUTL}.
v2:
* updated for scc_pata
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
395 lines
12 KiB
C
395 lines
12 KiB
C
/*
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* linux/drivers/ide/pci/opti621.c Version 0.7 Sept 10, 2002
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*
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* Copyright (C) 1996-1998 Linus Torvalds & authors (see below)
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*/
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/*
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* Authors:
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* Jaromir Koutek <miri@punknet.cz>,
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* Jan Harkes <jaharkes@cwi.nl>,
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* Mark Lord <mlord@pobox.com>
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* Some parts of code are from ali14xx.c and from rz1000.c.
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*
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* OPTi is trademark of OPTi, Octek is trademark of Octek.
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*
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* I used docs from OPTi databook, from ftp.opti.com, file 9123-0002.ps
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* and disassembled/traced setupvic.exe (DOS program).
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* It increases kernel code about 2 kB.
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* I don't have this card no more, but I hope I can get some in case
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* of needed development.
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* My card is Octek PIDE 1.01 (on card) or OPTiViC (program).
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* It has a place for a secondary connector in circuit, but nothing
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* is there. Also BIOS says no address for
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* secondary controller (see bellow in ide_init_opti621).
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* I've only tested this on my system, which only has one disk.
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* It's Western Digital WDAC2850, with PIO mode 3. The PCI bus
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* is at 20 MHz (I have DX2/80, I tried PCI at 40, but I got random
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* lockups). I tried the OCTEK double speed CD-ROM and
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* it does not work! But I can't boot DOS also, so it's probably
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* hardware fault. I have connected Conner 80MB, the Seagate 850MB (no
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* problems) and Seagate 1GB (as slave, WD as master). My experiences
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* with the third, 1GB drive: I got 3MB/s (hdparm), but sometimes
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* it slows to about 100kB/s! I don't know why and I have
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* not this drive now, so I can't try it again.
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* I write this driver because I lost the paper ("manual") with
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* settings of jumpers on the card and I have to boot Linux with
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* Loadlin except LILO, cause I have to run the setupvic.exe program
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* already or I get disk errors (my test: rpm -Vf
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* /usr/X11R6/bin/XF86_SVGA - or any big file).
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* Some numbers from hdparm -t /dev/hda:
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* Timing buffer-cache reads: 32 MB in 3.02 seconds =10.60 MB/sec
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* Timing buffered disk reads: 16 MB in 5.52 seconds = 2.90 MB/sec
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* I have 4 Megs/s before, but I don't know why (maybe changes
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* in hdparm test).
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* After release of 0.1, I got some successful reports, so it might work.
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*
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* The main problem with OPTi is that some timings for master
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* and slave must be the same. For example, if you have master
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* PIO 3 and slave PIO 0, driver have to set some timings of
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* master for PIO 0. Second problem is that opti621_tune_drive
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* got only one drive to set, but have to set both drives.
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* This is solved in compute_pios. If you don't set
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* the second drive, compute_pios use ide_get_best_pio_mode
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* for autoselect mode (you can change it to PIO 0, if you want).
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* If you then set the second drive to another PIO, the old value
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* (automatically selected) will be overrided by yours.
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* There is a 25/33MHz switch in configuration
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* register, but driver is written for use at any frequency which get
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* (use idebus=xx to select PCI bus speed).
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* Use ide0=autotune for automatical tune of the PIO modes.
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* If you get strange results, do not use this and set PIO manually
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* by hdparm.
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*
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* Version 0.1, Nov 8, 1996
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* by Jaromir Koutek, for 2.1.8.
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* Initial version of driver.
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*
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* Version 0.2
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* Number 0.2 skipped.
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*
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* Version 0.3, Nov 29, 1997
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* by Mark Lord (probably), for 2.1.68
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* Updates for use with new IDE block driver.
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*
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* Version 0.4, Dec 14, 1997
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* by Jan Harkes
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* Fixed some errors and cleaned the code.
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*
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* Version 0.5, Jan 2, 1998
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* by Jaromir Koutek
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* Updates for use with (again) new IDE block driver.
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* Update of documentation.
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*
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* Version 0.6, Jan 2, 1999
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* by Jaromir Koutek
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* Reversed to version 0.3 of the driver, because
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* 0.5 doesn't work.
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*/
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#undef REALLY_SLOW_IO /* most systems can safely undef this */
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#define OPTI621_DEBUG /* define for debug messages */
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/timer.h>
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#include <linux/mm.h>
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#include <linux/ioport.h>
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#include <linux/blkdev.h>
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#include <linux/pci.h>
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#include <linux/hdreg.h>
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#include <linux/ide.h>
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#include <asm/io.h>
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#define OPTI621_MAX_PIO 3
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/* In fact, I do not have any PIO 4 drive
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* (address: 25 ns, data: 70 ns, recovery: 35 ns),
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* but OPTi 82C621 is programmable and it can do (minimal values):
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* on 40MHz PCI bus (pulse 25 ns):
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* address: 25 ns, data: 25 ns, recovery: 50 ns;
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* on 20MHz PCI bus (pulse 50 ns):
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* address: 50 ns, data: 50 ns, recovery: 100 ns.
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*/
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/* #define READ_PREFETCH 0 */
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/* Uncomment for disable read prefetch.
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* There is some readprefetch capatibility in hdparm,
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* but when I type hdparm -P 1 /dev/hda, I got errors
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* and till reset drive is inaccessible.
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* This (hw) read prefetch is safe on my drive.
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*/
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#ifndef READ_PREFETCH
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#define READ_PREFETCH 0x40 /* read prefetch is enabled */
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#endif /* else read prefetch is disabled */
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#define READ_REG 0 /* index of Read cycle timing register */
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#define WRITE_REG 1 /* index of Write cycle timing register */
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#define CNTRL_REG 3 /* index of Control register */
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#define STRAP_REG 5 /* index of Strap register */
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#define MISC_REG 6 /* index of Miscellaneous register */
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static int reg_base;
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#define PIO_NOT_EXIST 254
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#define PIO_DONT_KNOW 255
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/* there are stored pio numbers from other calls of opti621_tune_drive */
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static void compute_pios(ide_drive_t *drive, u8 pio)
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/* Store values into drive->drive_data
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* second_contr - 0 for primary controller, 1 for secondary
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* slave_drive - 0 -> pio is for master, 1 -> pio is for slave
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* pio - PIO mode for selected drive (for other we don't know)
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*/
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{
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int d;
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ide_hwif_t *hwif = HWIF(drive);
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drive->drive_data = ide_get_best_pio_mode(drive, pio, OPTI621_MAX_PIO, NULL);
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for (d = 0; d < 2; ++d) {
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drive = &hwif->drives[d];
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if (drive->present) {
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if (drive->drive_data == PIO_DONT_KNOW)
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drive->drive_data = ide_get_best_pio_mode(drive, 255, OPTI621_MAX_PIO, NULL);
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#ifdef OPTI621_DEBUG
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printk("%s: Selected PIO mode %d\n",
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drive->name, drive->drive_data);
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#endif
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} else {
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drive->drive_data = PIO_NOT_EXIST;
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}
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}
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}
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static int cmpt_clk(int time, int bus_speed)
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/* Returns (rounded up) time in clocks for time in ns,
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* with bus_speed in MHz.
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* Example: bus_speed = 40 MHz, time = 80 ns
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* 1000/40 = 25 ns (clk value),
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* 80/25 = 3.2, rounded up to 4 (I hope ;-)).
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* Use idebus=xx to select right frequency.
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*/
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{
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return ((time*bus_speed+999)/1000);
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}
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/* Write value to register reg, base of register
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* is at reg_base (0x1f0 primary, 0x170 secondary,
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* if not changed by PCI configuration).
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* This is from setupvic.exe program.
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*/
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static void write_reg(u8 value, int reg)
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{
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inw(reg_base + 1);
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inw(reg_base + 1);
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outb(3, reg_base + 2);
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outb(value, reg_base + reg);
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outb(0x83, reg_base + 2);
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}
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/* Read value from register reg, base of register
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* is at reg_base (0x1f0 primary, 0x170 secondary,
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* if not changed by PCI configuration).
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* This is from setupvic.exe program.
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*/
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static u8 read_reg(int reg)
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{
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u8 ret = 0;
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inw(reg_base + 1);
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inw(reg_base + 1);
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outb(3, reg_base + 2);
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ret = inb(reg_base + reg);
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outb(0x83, reg_base + 2);
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return ret;
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}
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typedef struct pio_clocks_s {
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int address_time; /* Address setup (clocks) */
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int data_time; /* Active/data pulse (clocks) */
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int recovery_time; /* Recovery time (clocks) */
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} pio_clocks_t;
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static void compute_clocks(int pio, pio_clocks_t *clks)
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{
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if (pio != PIO_NOT_EXIST) {
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int adr_setup, data_pls;
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int bus_speed = system_bus_clock();
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adr_setup = ide_pio_timings[pio].setup_time;
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data_pls = ide_pio_timings[pio].active_time;
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clks->address_time = cmpt_clk(adr_setup, bus_speed);
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clks->data_time = cmpt_clk(data_pls, bus_speed);
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clks->recovery_time = cmpt_clk(ide_pio_timings[pio].cycle_time
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- adr_setup-data_pls, bus_speed);
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if (clks->address_time<1) clks->address_time = 1;
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if (clks->address_time>4) clks->address_time = 4;
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if (clks->data_time<1) clks->data_time = 1;
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if (clks->data_time>16) clks->data_time = 16;
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if (clks->recovery_time<2) clks->recovery_time = 2;
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if (clks->recovery_time>17) clks->recovery_time = 17;
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} else {
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clks->address_time = 1;
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clks->data_time = 1;
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clks->recovery_time = 2;
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/* minimal values */
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}
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}
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/* Main tune procedure, called from tuneproc. */
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static void opti621_tune_drive (ide_drive_t *drive, u8 pio)
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{
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/* primary and secondary drives share some registers,
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* so we have to program both drives
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*/
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unsigned long flags;
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u8 pio1 = 0, pio2 = 0;
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pio_clocks_t first, second;
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int ax, drdy;
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u8 cycle1, cycle2, misc;
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ide_hwif_t *hwif = HWIF(drive);
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/* sets drive->drive_data for both drives */
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compute_pios(drive, pio);
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pio1 = hwif->drives[0].drive_data;
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pio2 = hwif->drives[1].drive_data;
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compute_clocks(pio1, &first);
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compute_clocks(pio2, &second);
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/* ax = max(a1,a2) */
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ax = (first.address_time < second.address_time) ? second.address_time : first.address_time;
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drdy = 2; /* DRDY is default 2 (by OPTi Databook) */
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cycle1 = ((first.data_time-1)<<4) | (first.recovery_time-2);
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cycle2 = ((second.data_time-1)<<4) | (second.recovery_time-2);
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misc = READ_PREFETCH | ((ax-1)<<4) | ((drdy-2)<<1);
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#ifdef OPTI621_DEBUG
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printk("%s: master: address: %d, data: %d, "
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"recovery: %d, drdy: %d [clk]\n",
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hwif->name, ax, first.data_time,
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first.recovery_time, drdy);
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printk("%s: slave: address: %d, data: %d, "
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"recovery: %d, drdy: %d [clk]\n",
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hwif->name, ax, second.data_time,
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second.recovery_time, drdy);
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#endif
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spin_lock_irqsave(&ide_lock, flags);
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reg_base = hwif->io_ports[IDE_DATA_OFFSET];
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/* allow Register-B */
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outb(0xc0, reg_base + CNTRL_REG);
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/* hmm, setupvic.exe does this ;-) */
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outb(0xff, reg_base + 5);
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/* if reads 0xff, adapter not exist? */
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(void)inb(reg_base + CNTRL_REG);
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/* if reads 0xc0, no interface exist? */
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read_reg(CNTRL_REG);
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/* read version, probably 0 */
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read_reg(STRAP_REG);
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/* program primary drive */
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/* select Index-0 for Register-A */
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write_reg(0, MISC_REG);
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/* set read cycle timings */
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write_reg(cycle1, READ_REG);
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/* set write cycle timings */
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write_reg(cycle1, WRITE_REG);
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/* program secondary drive */
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/* select Index-1 for Register-B */
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write_reg(1, MISC_REG);
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/* set read cycle timings */
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write_reg(cycle2, READ_REG);
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/* set write cycle timings */
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write_reg(cycle2, WRITE_REG);
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/* use Register-A for drive 0 */
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/* use Register-B for drive 1 */
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write_reg(0x85, CNTRL_REG);
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/* set address setup, DRDY timings, */
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/* and read prefetch for both drives */
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write_reg(misc, MISC_REG);
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spin_unlock_irqrestore(&ide_lock, flags);
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}
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/*
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* init_hwif_opti621() is called once for each hwif found at boot.
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*/
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static void __devinit init_hwif_opti621 (ide_hwif_t *hwif)
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{
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hwif->autodma = 0;
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hwif->drives[0].drive_data = PIO_DONT_KNOW;
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hwif->drives[1].drive_data = PIO_DONT_KNOW;
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hwif->tuneproc = &opti621_tune_drive;
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if (!(hwif->dma_base))
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return;
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hwif->atapi_dma = 1;
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hwif->mwdma_mask = 0x07;
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hwif->swdma_mask = 0x07;
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if (!noautodma)
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hwif->autodma = 1;
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hwif->drives[0].autodma = hwif->autodma;
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hwif->drives[1].autodma = hwif->autodma;
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}
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static ide_pci_device_t opti621_chipsets[] __devinitdata = {
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{ /* 0 */
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.name = "OPTI621",
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.init_hwif = init_hwif_opti621,
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.channels = 2,
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.autodma = AUTODMA,
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.enablebits = {{0x45,0x80,0x00}, {0x40,0x08,0x00}},
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.bootable = ON_BOARD,
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},{ /* 1 */
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.name = "OPTI621X",
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.init_hwif = init_hwif_opti621,
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.channels = 2,
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.autodma = AUTODMA,
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.enablebits = {{0x45,0x80,0x00}, {0x40,0x08,0x00}},
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.bootable = ON_BOARD,
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}
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};
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static int __devinit opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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return ide_setup_pci_device(dev, &opti621_chipsets[id->driver_data]);
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}
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static struct pci_device_id opti621_pci_tbl[] = {
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{ PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
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{ PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, opti621_pci_tbl);
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static struct pci_driver driver = {
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.name = "Opti621_IDE",
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.id_table = opti621_pci_tbl,
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.probe = opti621_init_one,
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};
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static int __init opti621_ide_init(void)
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{
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return ide_pci_register_driver(&driver);
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}
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module_init(opti621_ide_init);
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MODULE_AUTHOR("Jaromir Koutek, Jan Harkes, Mark Lord");
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MODULE_DESCRIPTION("PCI driver module for Opti621 IDE");
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MODULE_LICENSE("GPL");
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