3060e9f0d1
The ARM architecture defines the memory locations that are permitted
to be accessed as the result of a speculative instruction fetch from
an exception level for which all stages of translation are disabled.
Specifically, the core is permitted to speculatively fetch from the
4KB region containing the current program counter 4K and next 4K.
When translation is changed from enabled to disabled for the running
exception level (SCTLR_ELn[M] changed from a value of 1 to 0), the
Falkor core may errantly speculatively access memory locations outside
of the 4KB region permitted by the architecture. The errant memory
access may lead to one of the following unexpected behaviors.
1) A System Error Interrupt (SEI) being raised by the Falkor core due
to the errant memory access attempting to access a region of memory
that is protected by a slave-side memory protection unit.
2) Unpredictable device behavior due to a speculative read from device
memory. This behavior may only occur if the instruction cache is
disabled prior to or coincident with translation being changed from
enabled to disabled.
The conditions leading to this erratum will not occur when either of the
following occur:
1) A higher exception level disables translation of a lower exception level
(e.g. EL2 changing SCTLR_EL1[M] from a value of 1 to 0).
2) An exception level disabling its stage-1 translation if its stage-2
translation is enabled (e.g. EL1 changing SCTLR_EL1[M] from a value of 1
to 0 when HCR_EL2[VM] has a value of 1).
To avoid the errant behavior, software must execute an ISB immediately
prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0.
Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
55 lines
1.4 KiB
ArmAsm
55 lines
1.4 KiB
ArmAsm
/*
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* CPU reset routines
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2015 Huawei Futurewei Technologies.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/sysreg.h>
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#include <asm/virt.h>
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.text
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.pushsection .idmap.text, "ax"
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/*
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* __cpu_soft_restart(el2_switch, entry, arg0, arg1, arg2) - Helper for
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* cpu_soft_restart.
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*
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* @el2_switch: Flag to indicate a swich to EL2 is needed.
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* @entry: Location to jump to for soft reset.
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* arg0: First argument passed to @entry.
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* arg1: Second argument passed to @entry.
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* arg2: Third argument passed to @entry.
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*
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* Put the CPU into the same state as it would be if it had been reset, and
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* branch to what would be the reset vector. It must be executed with the
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* flat identity mapping.
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*/
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ENTRY(__cpu_soft_restart)
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/* Clear sctlr_el1 flags. */
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mrs x12, sctlr_el1
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ldr x13, =SCTLR_ELx_FLAGS
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bic x12, x12, x13
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pre_disable_mmu_workaround
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msr sctlr_el1, x12
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isb
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cbz x0, 1f // el2_switch?
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mov x0, #HVC_SOFT_RESTART
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hvc #0 // no return
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1: mov x18, x1 // entry
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mov x0, x2 // arg0
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mov x1, x3 // arg1
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mov x2, x4 // arg2
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br x18
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ENDPROC(__cpu_soft_restart)
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.popsection
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