a8d4636f96
The CCSIDR_EL1.{NumSets,Associativity,LineSize} fields are only for use
in conjunction with set/way cache maintenance and are not guaranteed to
represent the actual microarchitectural features of a design.
The architecture explicitly states:
| You cannot make any inference about the actual sizes of caches based
| on these parameters.
Furthermore, CCSIDR_EL1.{WT,WB,RA,WA} have been removed retrospectively
from ARMv8 and are now considered to be UNKNOWN.
Since the kernel doesn't make use of set/way cache maintenance and it is
not possible for userspace to execute these instructions, we have no
need for the CCSIDR information in the kernel.
This patch removes the accessors, along with the related portions of the
cacheinfo support, which should instead be reintroduced when firmware has
a mechanism to provide us with reliable information.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
99 lines
2.9 KiB
C
99 lines
2.9 KiB
C
/*
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* ARM64 cacheinfo support
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*
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* Copyright (C) 2015 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/cacheinfo.h>
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#include <linux/of.h>
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#define MAX_CACHE_LEVEL 7 /* Max 7 level supported */
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/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
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#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1))
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#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level))
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#define CLIDR_CTYPE(clidr, level) \
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(((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
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static inline enum cache_type get_cache_type(int level)
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{
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u64 clidr;
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if (level > MAX_CACHE_LEVEL)
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return CACHE_TYPE_NOCACHE;
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clidr = read_sysreg(clidr_el1);
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return CLIDR_CTYPE(clidr, level);
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}
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static void ci_leaf_init(struct cacheinfo *this_leaf,
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enum cache_type type, unsigned int level)
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{
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this_leaf->level = level;
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this_leaf->type = type;
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}
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static int __init_cache_level(unsigned int cpu)
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{
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unsigned int ctype, level, leaves, of_level;
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struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
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for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) {
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ctype = get_cache_type(level);
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if (ctype == CACHE_TYPE_NOCACHE) {
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level--;
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break;
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}
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/* Separate instruction and data caches */
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leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1;
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}
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of_level = of_find_last_cache_level(cpu);
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if (level < of_level) {
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/*
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* some external caches not specified in CLIDR_EL1
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* the information may be available in the device tree
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* only unified external caches are considered here
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*/
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leaves += (of_level - level);
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level = of_level;
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}
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this_cpu_ci->num_levels = level;
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this_cpu_ci->num_leaves = leaves;
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return 0;
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}
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static int __populate_cache_leaves(unsigned int cpu)
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{
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unsigned int level, idx;
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enum cache_type type;
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struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
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struct cacheinfo *this_leaf = this_cpu_ci->info_list;
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for (idx = 0, level = 1; level <= this_cpu_ci->num_levels &&
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idx < this_cpu_ci->num_leaves; idx++, level++) {
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type = get_cache_type(level);
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if (type == CACHE_TYPE_SEPARATE) {
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ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
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ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
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} else {
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ci_leaf_init(this_leaf++, type, level);
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}
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}
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return 0;
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}
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DEFINE_SMP_CALL_CACHE_FUNCTION(init_cache_level)
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DEFINE_SMP_CALL_CACHE_FUNCTION(populate_cache_leaves)
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