1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
23 lines
1.2 KiB
Text
23 lines
1.2 KiB
Text
1. Need to figure out why PCI writes to the IOC3 hang, and if it is okay
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not to write to the IOC3 ever.
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2. Need to figure out RRB allocation in bridge_startup().
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3. Need to figure out why address swaizzling is needed in inw/outw for
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Qlogic scsi controllers.
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4. Need to integrate ip27-klconfig.c:find_lboard and
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ip27-init.c:find_lbaord_real. DONE
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5. Is it okay to set calias space on all nodes as 0, instead of 8k as
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in irix?
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6. Investigate why things do not work without the setup_test() call
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being invoked on all nodes in ip27-memory.c.
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7. Too many CLIs in the locore handlers :
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For the low level handlers set up by set_except_vector(),
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__tlb_refill_debug_tramp, __xtlb_refill_debug_tramp and cacheerror,
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investigate whether the code should do CLI, STI or KMODE.
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8. Too many do_page_faults invoked - investigate.
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9. start_thread must turn off UX64 ... and define tlb_refill_debug.
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10. Need a bad pmd table, bad pte table. __bad_pmd_table/__bad_pagetable
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does not agree with pgd_bad/pmd_bad.
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11. All intrs (ip27_do_irq handlers) are targetted at cpu A on the node.
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This might need to change later. Only the timer intr is set up to be
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received on both Cpu A and B. (ip27_do_irq()/bridge_startup())
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13. Cache flushing (specially the SMP version) has to be investigated.
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