b920de1b77
Add architecture support for the MN10300/AM33 CPUs produced by MEI to the kernel. This patch also adds board support for the ASB2303 with the ASB2308 daughter board, and the ASB2305. The only processor supported is the MN103E010, which is an AM33v2 core plus on-chip devices. [akpm@linux-foundation.org: nuke cvs control strings] Signed-off-by: Masakazu Urade <urade.masakazu@jp.panasonic.com> Signed-off-by: Koichi Yasutake <yasutake.koichi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
136 lines
3.5 KiB
C
136 lines
3.5 KiB
C
/* MN10300 Unaligned memory access handling
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#ifndef _ASM_UNALIGNED_H
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#define _ASM_UNALIGNED_H
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#include <asm/types.h>
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#if 0
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extern int __bug_unaligned_x(void *ptr);
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/*
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* What is the most efficient way of loading/storing an unaligned value?
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*
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* That is the subject of this file. Efficiency here is defined as
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* minimum code size with minimum register usage for the common cases.
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* It is currently not believed that long longs are common, so we
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* trade efficiency for the chars, shorts and longs against the long
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* longs.
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*
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* Current stats with gcc 2.7.2.2 for these functions:
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*
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* ptrsize get: code regs put: code regs
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* 1 1 1 1 2
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* 2 3 2 3 2
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* 4 7 3 7 3
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* 8 20 6 16 6
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*
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* gcc 2.95.1 seems to code differently:
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*
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* ptrsize get: code regs put: code regs
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* 1 1 1 1 2
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* 2 3 2 3 2
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* 4 7 4 7 4
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* 8 19 8 15 6
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*
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* which may or may not be more efficient (depending upon whether
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* you can afford the extra registers). Hopefully the gcc 2.95
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* is inteligent enough to decide if it is better to use the
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* extra register, but evidence so far seems to suggest otherwise.
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*
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* Unfortunately, gcc is not able to optimise the high word
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* out of long long >> 32, or the low word from long long << 32
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*/
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#define __get_unaligned_2(__p) \
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(__p[0] | __p[1] << 8)
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#define __get_unaligned_4(__p) \
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(__p[0] | __p[1] << 8 | __p[2] << 16 | __p[3] << 24)
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#define get_unaligned(ptr) \
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({ \
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unsigned int __v1, __v2; \
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__typeof__(*(ptr)) __v; \
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__u8 *__p = (__u8 *)(ptr); \
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\
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switch (sizeof(*(ptr))) { \
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case 1: __v = *(ptr); break; \
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case 2: __v = __get_unaligned_2(__p); break; \
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case 4: __v = __get_unaligned_4(__p); break; \
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case 8: \
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__v2 = __get_unaligned_4((__p+4)); \
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__v1 = __get_unaligned_4(__p); \
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__v = ((unsigned long long)__v2 << 32 | __v1); \
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break; \
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default: __v = __bug_unaligned_x(__p); break; \
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} \
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__v; \
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})
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static inline void __put_unaligned_2(__u32 __v, register __u8 *__p)
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{
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*__p++ = __v;
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*__p++ = __v >> 8;
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}
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static inline void __put_unaligned_4(__u32 __v, register __u8 *__p)
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{
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__put_unaligned_2(__v >> 16, __p + 2);
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__put_unaligned_2(__v, __p);
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}
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static inline void __put_unaligned_8(const unsigned long long __v, __u8 *__p)
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{
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/*
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* tradeoff: 8 bytes of stack for all unaligned puts (2
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* instructions), or an extra register in the long long
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* case - go for the extra register.
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*/
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__put_unaligned_4(__v >> 32, __p + 4);
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__put_unaligned_4(__v, __p);
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}
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/*
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* Try to store an unaligned value as efficiently as possible.
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*/
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#define put_unaligned(val, ptr) \
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({ \
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switch (sizeof(*(ptr))) { \
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case 1: \
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*(ptr) = (val); \
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break; \
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case 2: \
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__put_unaligned_2((val), (__u8 *)(ptr)); \
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break; \
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case 4: \
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__put_unaligned_4((val), (__u8 *)(ptr)); \
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break; \
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case 8: \
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__put_unaligned_8((val), (__u8 *)(ptr)); \
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break; \
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default: \
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__bug_unaligned_x(ptr); \
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break; \
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} \
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(void) 0; \
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})
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#else
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#define get_unaligned(ptr) (*(ptr))
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#define put_unaligned(val, ptr) ({ *(ptr) = (val); (void) 0; })
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#endif
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#endif
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