74bf4312ff
We now use the TSB hardware assist features of the UltraSPARC MMUs. SMP is currently knowingly broken, we need to find another place to store the per-cpu base pointers. We hid them away in the TSB base register, and that obviously will not work any more :-) Another known broken case is non-8KB base page size. Also noticed that flush_tlb_all() is not referenced anywhere, only the internal __flush_tlb_all() (local cpu only) is used by the sparc64 port, so we can get rid of flush_tlb_all(). The kernel gets it's own 8KB TSB (swapper_tsb) and each address space gets it's own private 8K TSB. Later we can add code to dynamically increase the size of per-process TSB as the RSS grows. An 8KB TSB is good enough for up to about a 4MB RSS, after which the TSB starts to incur many capacity and conflict misses. We even accumulate OBP translations into the kernel TSB. Another area for refinement is large page size support. We could use a secondary address space TSB to handle those. Signed-off-by: David S. Miller <davem@davemloft.net>
93 lines
1.8 KiB
C
93 lines
1.8 KiB
C
/* arch/sparc64/mm/tlb.c
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*
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* Copyright (C) 2004 David S. Miller <davem@redhat.com>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/percpu.h>
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#include <linux/mm.h>
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#include <linux/swap.h>
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#include <asm/pgtable.h>
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#include <asm/pgalloc.h>
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#include <asm/tlbflush.h>
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#include <asm/cacheflush.h>
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#include <asm/mmu_context.h>
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#include <asm/tlb.h>
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/* Heavily inspired by the ppc64 code. */
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DEFINE_PER_CPU(struct mmu_gather, mmu_gathers) = { 0, };
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void flush_tlb_pending(void)
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{
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struct mmu_gather *mp = &__get_cpu_var(mmu_gathers);
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if (mp->tlb_nr) {
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flush_tsb_user(mp);
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if (CTX_VALID(mp->mm->context)) {
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#ifdef CONFIG_SMP
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smp_flush_tlb_pending(mp->mm, mp->tlb_nr,
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&mp->vaddrs[0]);
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#else
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__flush_tlb_pending(CTX_HWBITS(mp->mm->context),
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mp->tlb_nr, &mp->vaddrs[0]);
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#endif
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}
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mp->tlb_nr = 0;
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}
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}
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void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig)
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{
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struct mmu_gather *mp = &__get_cpu_var(mmu_gathers);
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unsigned long nr;
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vaddr &= PAGE_MASK;
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if (pte_exec(orig))
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vaddr |= 0x1UL;
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if (pte_dirty(orig)) {
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unsigned long paddr, pfn = pte_pfn(orig);
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struct address_space *mapping;
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struct page *page;
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if (!pfn_valid(pfn))
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goto no_cache_flush;
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page = pfn_to_page(pfn);
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if (PageReserved(page))
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goto no_cache_flush;
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/* A real file page? */
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mapping = page_mapping(page);
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if (!mapping)
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goto no_cache_flush;
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paddr = (unsigned long) page_address(page);
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if ((paddr ^ vaddr) & (1 << 13))
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flush_dcache_page_all(mm, page);
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}
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no_cache_flush:
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if (mp->fullmm)
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return;
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nr = mp->tlb_nr;
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if (unlikely(nr != 0 && mm != mp->mm)) {
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flush_tlb_pending();
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nr = 0;
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}
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if (nr == 0)
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mp->mm = mm;
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mp->vaddrs[nr] = vaddr;
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mp->tlb_nr = ++nr;
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if (nr >= TLB_BATCH_NR)
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flush_tlb_pending();
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}
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