acb15c85de
We found an issue in pal.S. According to the software runtime SPEC, The caller's output registers do not need to be preserved for caller. The callee may reuse input registers for any other purpose within the procedure. in ia64_pal_call_phys_stacked, input registers are copied to output registers before call into ia64_switch_mode_phys, then used to call into PAL. This assumes output registers are preserved in ia64_switch_mode_phys, which may not be true. In this particular case, ia64_switch_mode_phys alloc a null frame , and mask off psr.i. If an interrupt comes at this small window, or an MCA comes inside the procedure, output registers maybe changed, then the pal call may got some staled input registers. This patch moves the copies from input to output after ia64_switch_mode_phys to follow the software runtime convention. It also removed some unused labels in ia64_pal_call_phys_stacked. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
302 lines
7.5 KiB
ArmAsm
302 lines
7.5 KiB
ArmAsm
/*
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* PAL Firmware support
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* IA-64 Processor Programmers Reference Vol 2
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*
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* Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
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* Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
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* Copyright (C) 1999-2001, 2003 Hewlett-Packard Co
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* David Mosberger <davidm@hpl.hp.com>
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* Stephane Eranian <eranian@hpl.hp.com>
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*
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* 05/22/2000 eranian Added support for stacked register calls
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* 05/24/2000 eranian Added support for physical mode static calls
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*/
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#include <asm/asmmacro.h>
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#include <asm/processor.h>
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.data
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pal_entry_point:
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data8 ia64_pal_default_handler
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.text
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/*
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* Set the PAL entry point address. This could be written in C code, but we do it here
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* to keep it all in one module (besides, it's so trivial that it's
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* not a big deal).
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*
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* in0 Address of the PAL entry point (text address, NOT a function descriptor).
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*/
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GLOBAL_ENTRY(ia64_pal_handler_init)
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alloc r3=ar.pfs,1,0,0,0
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movl r2=pal_entry_point
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;;
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st8 [r2]=in0
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br.ret.sptk.many rp
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END(ia64_pal_handler_init)
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/*
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* Default PAL call handler. This needs to be coded in assembly because it uses
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* the static calling convention, i.e., the RSE may not be used and calls are
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* done via "br.cond" (not "br.call").
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*/
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GLOBAL_ENTRY(ia64_pal_default_handler)
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mov r8=-1
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br.cond.sptk.many rp
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END(ia64_pal_default_handler)
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/*
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* Make a PAL call using the static calling convention.
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*
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* in0 Index of PAL service
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* in1 - in3 Remaining PAL arguments
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* in4 1 ==> clear psr.ic, 0 ==> don't clear psr.ic
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*
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*/
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GLOBAL_ENTRY(ia64_pal_call_static)
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.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(5)
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alloc loc1 = ar.pfs,5,5,0,0
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movl loc2 = pal_entry_point
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1: {
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mov r28 = in0
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mov r29 = in1
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mov r8 = ip
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}
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;;
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ld8 loc2 = [loc2] // loc2 <- entry point
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tbit.nz p6,p7 = in4, 0
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adds r8 = 1f-1b,r8
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mov loc4=ar.rsc // save RSE configuration
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;;
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mov ar.rsc=0 // put RSE in enforced lazy, LE mode
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mov loc3 = psr
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mov loc0 = rp
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.body
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mov r30 = in2
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(p6) rsm psr.i | psr.ic
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mov r31 = in3
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mov b7 = loc2
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(p7) rsm psr.i
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;;
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(p6) srlz.i
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mov rp = r8
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br.cond.sptk.many b7
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1: mov psr.l = loc3
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mov ar.rsc = loc4 // restore RSE configuration
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mov ar.pfs = loc1
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mov rp = loc0
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;;
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srlz.d // seralize restoration of psr.l
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br.ret.sptk.many b0
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END(ia64_pal_call_static)
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/*
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* Make a PAL call using the stacked registers calling convention.
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*
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* Inputs:
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* in0 Index of PAL service
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* in2 - in3 Remaning PAL arguments
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*/
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GLOBAL_ENTRY(ia64_pal_call_stacked)
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.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(4)
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alloc loc1 = ar.pfs,4,4,4,0
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movl loc2 = pal_entry_point
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mov r28 = in0 // Index MUST be copied to r28
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mov out0 = in0 // AND in0 of PAL function
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mov loc0 = rp
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.body
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;;
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ld8 loc2 = [loc2] // loc2 <- entry point
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mov out1 = in1
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mov out2 = in2
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mov out3 = in3
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mov loc3 = psr
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;;
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rsm psr.i
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mov b7 = loc2
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;;
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br.call.sptk.many rp=b7 // now make the call
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.ret0: mov psr.l = loc3
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mov ar.pfs = loc1
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mov rp = loc0
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;;
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srlz.d // serialize restoration of psr.l
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br.ret.sptk.many b0
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END(ia64_pal_call_stacked)
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/*
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* Make a physical mode PAL call using the static registers calling convention.
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*
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* Inputs:
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* in0 Index of PAL service
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* in2 - in3 Remaning PAL arguments
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*
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* PSR_LP, PSR_TB, PSR_ID, PSR_DA are never set by the kernel.
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* So we don't need to clear them.
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*/
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#define PAL_PSR_BITS_TO_CLEAR \
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(IA64_PSR_I | IA64_PSR_IT | IA64_PSR_DT | IA64_PSR_DB | IA64_PSR_RT | \
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IA64_PSR_DD | IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED | \
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IA64_PSR_DFL | IA64_PSR_DFH)
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#define PAL_PSR_BITS_TO_SET \
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(IA64_PSR_BN)
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GLOBAL_ENTRY(ia64_pal_call_phys_static)
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.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(4)
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alloc loc1 = ar.pfs,4,7,0,0
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movl loc2 = pal_entry_point
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1: {
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mov r28 = in0 // copy procedure index
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mov r8 = ip // save ip to compute branch
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mov loc0 = rp // save rp
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}
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.body
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;;
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ld8 loc2 = [loc2] // loc2 <- entry point
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mov r29 = in1 // first argument
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mov r30 = in2 // copy arg2
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mov r31 = in3 // copy arg3
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;;
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mov loc3 = psr // save psr
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adds r8 = 1f-1b,r8 // calculate return address for call
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;;
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mov loc4=ar.rsc // save RSE configuration
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dep.z loc2=loc2,0,61 // convert pal entry point to physical
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tpa r8=r8 // convert rp to physical
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;;
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mov b7 = loc2 // install target to branch reg
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mov ar.rsc=0 // put RSE in enforced lazy, LE mode
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movl r16=PAL_PSR_BITS_TO_CLEAR
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movl r17=PAL_PSR_BITS_TO_SET
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;;
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or loc3=loc3,r17 // add in psr the bits to set
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;;
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andcm r16=loc3,r16 // removes bits to clear from psr
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br.call.sptk.many rp=ia64_switch_mode_phys
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.ret1: mov rp = r8 // install return address (physical)
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mov loc5 = r19
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mov loc6 = r20
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br.cond.sptk.many b7
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1:
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mov ar.rsc=0 // put RSE in enforced lazy, LE mode
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mov r16=loc3 // r16= original psr
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mov r19=loc5
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mov r20=loc6
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br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
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.ret2:
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mov psr.l = loc3 // restore init PSR
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mov ar.pfs = loc1
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mov rp = loc0
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;;
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mov ar.rsc=loc4 // restore RSE configuration
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srlz.d // seralize restoration of psr.l
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br.ret.sptk.many b0
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END(ia64_pal_call_phys_static)
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/*
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* Make a PAL call using the stacked registers in physical mode.
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*
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* Inputs:
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* in0 Index of PAL service
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* in2 - in3 Remaning PAL arguments
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*/
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GLOBAL_ENTRY(ia64_pal_call_phys_stacked)
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.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(5)
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alloc loc1 = ar.pfs,5,7,4,0
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movl loc2 = pal_entry_point
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1: {
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mov r28 = in0 // copy procedure index
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mov loc0 = rp // save rp
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}
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.body
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;;
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ld8 loc2 = [loc2] // loc2 <- entry point
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mov loc3 = psr // save psr
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;;
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mov loc4=ar.rsc // save RSE configuration
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dep.z loc2=loc2,0,61 // convert pal entry point to physical
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;;
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mov ar.rsc=0 // put RSE in enforced lazy, LE mode
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movl r16=PAL_PSR_BITS_TO_CLEAR
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movl r17=PAL_PSR_BITS_TO_SET
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;;
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or loc3=loc3,r17 // add in psr the bits to set
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mov b7 = loc2 // install target to branch reg
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;;
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andcm r16=loc3,r16 // removes bits to clear from psr
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br.call.sptk.many rp=ia64_switch_mode_phys
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mov out0 = in0 // first argument
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mov out1 = in1 // copy arg2
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mov out2 = in2 // copy arg3
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mov out3 = in3 // copy arg3
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mov loc5 = r19
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mov loc6 = r20
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br.call.sptk.many rp=b7 // now make the call
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mov ar.rsc=0 // put RSE in enforced lazy, LE mode
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mov r16=loc3 // r16= original psr
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mov r19=loc5
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mov r20=loc6
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br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
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mov psr.l = loc3 // restore init PSR
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mov ar.pfs = loc1
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mov rp = loc0
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;;
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mov ar.rsc=loc4 // restore RSE configuration
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srlz.d // seralize restoration of psr.l
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br.ret.sptk.many b0
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END(ia64_pal_call_phys_stacked)
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/*
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* Save scratch fp scratch regs which aren't saved in pt_regs already (fp10-fp15).
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*
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* NOTE: We need to do this since firmware (SAL and PAL) may use any of the scratch
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* regs fp-low partition.
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*
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* Inputs:
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* in0 Address of stack storage for fp regs
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*/
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GLOBAL_ENTRY(ia64_save_scratch_fpregs)
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alloc r3=ar.pfs,1,0,0,0
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add r2=16,in0
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;;
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stf.spill [in0] = f10,32
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stf.spill [r2] = f11,32
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;;
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stf.spill [in0] = f12,32
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stf.spill [r2] = f13,32
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;;
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stf.spill [in0] = f14,32
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stf.spill [r2] = f15,32
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br.ret.sptk.many rp
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END(ia64_save_scratch_fpregs)
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/*
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* Load scratch fp scratch regs (fp10-fp15)
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*
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* Inputs:
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* in0 Address of stack storage for fp regs
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*/
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GLOBAL_ENTRY(ia64_load_scratch_fpregs)
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alloc r3=ar.pfs,1,0,0,0
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add r2=16,in0
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;;
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ldf.fill f10 = [in0],32
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ldf.fill f11 = [r2],32
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;;
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ldf.fill f12 = [in0],32
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ldf.fill f13 = [r2],32
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;;
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ldf.fill f14 = [in0],32
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ldf.fill f15 = [r2],32
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br.ret.sptk.many rp
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END(ia64_load_scratch_fpregs)
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