c46ea13f55
Replace existing hw_ranndom/exynos-rng driver with a new, reworked one. This is a driver for pseudo random number generator block which on Exynos4 chipsets must be seeded with some value. On newer Exynos5420 chipsets it might seed itself from true random number generator block but this is not implemented yet. New driver is a complete rework to use the crypto ALGAPI instead of hw_random API. Rationale for the change: 1. hw_random interface is for true RNG devices. 2. The old driver was seeding itself with jiffies which is not a reliable source for randomness. 3. Device generates five random 32-bit numbers in each pass but old driver was returning only one 32-bit number thus its performance was reduced. Compatibility with DeviceTree bindings is preserved. New driver does not use runtime power management but manually enables and disables the clock when needed. This is preferred approach because using runtime PM just to toggle clock is huge overhead. Another difference is reseeding itself with generated random data periodically and during resuming from system suspend (previously driver was re-seeding itself again with jiffies). Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Stephan Müller <smueller@chronox.de> Reviewed-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
41 lines
1.8 KiB
Makefile
41 lines
1.8 KiB
Makefile
obj-$(CONFIG_CRYPTO_DEV_ATMEL_AES) += atmel-aes.o
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obj-$(CONFIG_CRYPTO_DEV_ATMEL_SHA) += atmel-sha.o
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obj-$(CONFIG_CRYPTO_DEV_ATMEL_TDES) += atmel-tdes.o
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obj-$(CONFIG_CRYPTO_DEV_BFIN_CRC) += bfin_crc.o
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obj-$(CONFIG_CRYPTO_DEV_CAVIUM_ZIP) += cavium/
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obj-$(CONFIG_CRYPTO_DEV_CCP) += ccp/
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obj-$(CONFIG_CRYPTO_DEV_CHELSIO) += chelsio/
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obj-$(CONFIG_CRYPTO_DEV_CPT) += cavium/cpt/
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obj-$(CONFIG_CRYPTO_DEV_EXYNOS_RNG) += exynos-rng.o
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obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam/
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obj-$(CONFIG_CRYPTO_DEV_GEODE) += geode-aes.o
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obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o
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obj-$(CONFIG_CRYPTO_DEV_IMGTEC_HASH) += img-hash.o
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obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o
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obj-$(CONFIG_CRYPTO_DEV_MV_CESA) += mv_cesa.o
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obj-$(CONFIG_CRYPTO_DEV_MARVELL_CESA) += marvell/
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obj-$(CONFIG_CRYPTO_DEV_MEDIATEK) += mediatek/
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obj-$(CONFIG_CRYPTO_DEV_MXS_DCP) += mxs-dcp.o
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obj-$(CONFIG_CRYPTO_DEV_MXC_SCC) += mxc-scc.o
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obj-$(CONFIG_CRYPTO_DEV_NIAGARA2) += n2_crypto.o
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n2_crypto-y := n2_core.o n2_asm.o
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obj-$(CONFIG_CRYPTO_DEV_NX) += nx/
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obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o
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obj-$(CONFIG_CRYPTO_DEV_OMAP_DES) += omap-des.o
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obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o
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obj-$(CONFIG_CRYPTO_DEV_PADLOCK_AES) += padlock-aes.o
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obj-$(CONFIG_CRYPTO_DEV_PADLOCK_SHA) += padlock-sha.o
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obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o
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obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/
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obj-$(CONFIG_CRYPTO_DEV_QAT) += qat/
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obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/
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obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/
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obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
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obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
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obj-$(CONFIG_CRYPTO_DEV_STM32) += stm32/
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obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/
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obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
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obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
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obj-$(CONFIG_CRYPTO_DEV_VIRTIO) += virtio/
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obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/
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obj-$(CONFIG_CRYPTO_DEV_BCM_SPU) += bcm/
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