7db6a7fa09
This fixes the failure to register the IRQ_RTCAlrm alarm as a wakeup event. It is misinterpreted as a gpio irq not a PWER bitmask. Fixed this by converting the incorrect IRQ_TO_IRQ() to a correct version of irq_to_gpio(). Reported-by: Nick Bane <nickbane1@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
154 lines
4.8 KiB
C
154 lines
4.8 KiB
C
/*
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* arch/arm/mach-pxa/include/mach/gpio.h
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*
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* PXA GPIO wrappers for arch-neutral GPIO calls
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*
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* Written by Philipp Zabel <philipp.zabel@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef __ASM_ARCH_PXA_GPIO_H
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#define __ASM_ARCH_PXA_GPIO_H
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#include <mach/irqs.h>
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#include <mach/hardware.h>
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#include <asm-generic/gpio.h>
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#define GPIO_REGS_VIRT io_p2v(0x40E00000)
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#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
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#define GPIO_REG(x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x)))
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/* GPIO Pin Level Registers */
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#define GPLR0 GPIO_REG(BANK_OFF(0) + 0x00)
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#define GPLR1 GPIO_REG(BANK_OFF(1) + 0x00)
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#define GPLR2 GPIO_REG(BANK_OFF(2) + 0x00)
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#define GPLR3 GPIO_REG(BANK_OFF(3) + 0x00)
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/* GPIO Pin Direction Registers */
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#define GPDR0 GPIO_REG(BANK_OFF(0) + 0x0c)
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#define GPDR1 GPIO_REG(BANK_OFF(1) + 0x0c)
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#define GPDR2 GPIO_REG(BANK_OFF(2) + 0x0c)
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#define GPDR3 GPIO_REG(BANK_OFF(3) + 0x0c)
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/* GPIO Pin Output Set Registers */
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#define GPSR0 GPIO_REG(BANK_OFF(0) + 0x18)
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#define GPSR1 GPIO_REG(BANK_OFF(1) + 0x18)
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#define GPSR2 GPIO_REG(BANK_OFF(2) + 0x18)
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#define GPSR3 GPIO_REG(BANK_OFF(3) + 0x18)
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/* GPIO Pin Output Clear Registers */
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#define GPCR0 GPIO_REG(BANK_OFF(0) + 0x24)
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#define GPCR1 GPIO_REG(BANK_OFF(1) + 0x24)
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#define GPCR2 GPIO_REG(BANK_OFF(2) + 0x24)
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#define GPCR3 GPIO_REG(BANK_OFF(3) + 0x24)
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/* GPIO Rising Edge Detect Registers */
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#define GRER0 GPIO_REG(BANK_OFF(0) + 0x30)
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#define GRER1 GPIO_REG(BANK_OFF(1) + 0x30)
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#define GRER2 GPIO_REG(BANK_OFF(2) + 0x30)
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#define GRER3 GPIO_REG(BANK_OFF(3) + 0x30)
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/* GPIO Falling Edge Detect Registers */
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#define GFER0 GPIO_REG(BANK_OFF(0) + 0x3c)
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#define GFER1 GPIO_REG(BANK_OFF(1) + 0x3c)
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#define GFER2 GPIO_REG(BANK_OFF(2) + 0x3c)
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#define GFER3 GPIO_REG(BANK_OFF(3) + 0x3c)
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/* GPIO Edge Detect Status Registers */
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#define GEDR0 GPIO_REG(BANK_OFF(0) + 0x48)
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#define GEDR1 GPIO_REG(BANK_OFF(1) + 0x48)
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#define GEDR2 GPIO_REG(BANK_OFF(2) + 0x48)
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#define GEDR3 GPIO_REG(BANK_OFF(3) + 0x48)
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/* GPIO Alternate Function Select Registers */
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#define GAFR0_L GPIO_REG(0x0054)
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#define GAFR0_U GPIO_REG(0x0058)
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#define GAFR1_L GPIO_REG(0x005C)
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#define GAFR1_U GPIO_REG(0x0060)
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#define GAFR2_L GPIO_REG(0x0064)
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#define GAFR2_U GPIO_REG(0x0068)
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#define GAFR3_L GPIO_REG(0x006C)
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#define GAFR3_U GPIO_REG(0x0070)
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/* More handy macros. The argument is a literal GPIO number. */
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#define GPIO_bit(x) (1 << ((x) & 0x1f))
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#define GPLR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x00)
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#define GPDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x0c)
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#define GPSR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x18)
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#define GPCR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x24)
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#define GRER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x30)
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#define GFER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x3c)
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#define GEDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x48)
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#define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2))
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#define NR_BUILTIN_GPIO PXA_GPIO_IRQ_NUM
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#define gpio_to_bank(gpio) ((gpio) >> 5)
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#define gpio_to_irq(gpio) IRQ_GPIO(gpio)
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static inline int irq_to_gpio(unsigned int irq)
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{
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int gpio;
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if (irq == IRQ_GPIO0 || irq == IRQ_GPIO1)
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return irq - IRQ_GPIO0;
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gpio = irq - PXA_GPIO_IRQ_BASE;
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if (gpio >= 2 && gpio < NR_BUILTIN_GPIO)
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return gpio;
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return -1;
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}
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#ifdef CONFIG_CPU_PXA26x
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/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
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* as well as their Alternate Function value being '1' for GPIO in GAFRx.
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*/
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static inline int __gpio_is_inverted(unsigned gpio)
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{
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return cpu_is_pxa25x() && gpio > 85;
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}
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#else
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static inline int __gpio_is_inverted(unsigned gpio) { return 0; }
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#endif
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/*
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* On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
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* function of a GPIO, and GPDRx cannot be altered once configured. It
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* is attributed as "occupied" here (I know this terminology isn't
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* accurate, you are welcome to propose a better one :-)
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*/
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static inline int __gpio_is_occupied(unsigned gpio)
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{
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if (cpu_is_pxa27x() || cpu_is_pxa25x()) {
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int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3;
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int dir = GPDR(gpio) & GPIO_bit(gpio);
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if (__gpio_is_inverted(gpio))
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return af != 1 || dir == 0;
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else
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return af != 0 || dir != 0;
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} else
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return GPDR(gpio) & GPIO_bit(gpio);
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}
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#include <plat/gpio.h>
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#endif
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