672 lines
17 KiB
C
672 lines
17 KiB
C
/*
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*
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* Common boot and setup code.
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*
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* Copyright (C) 2001 PPC64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#undef DEBUG
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/reboot.h>
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#include <linux/delay.h>
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#include <linux/initrd.h>
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#include <linux/seq_file.h>
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#include <linux/ioport.h>
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#include <linux/console.h>
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#include <linux/utsname.h>
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#include <linux/tty.h>
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#include <linux/root_dev.h>
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#include <linux/notifier.h>
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#include <linux/cpu.h>
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#include <linux/unistd.h>
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#include <linux/serial.h>
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#include <linux/serial_8250.h>
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#include <linux/bootmem.h>
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#include <linux/pci.h>
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#include <linux/lockdep.h>
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#include <linux/memblock.h>
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#include <asm/io.h>
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#include <asm/kdump.h>
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#include <asm/prom.h>
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#include <asm/processor.h>
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#include <asm/pgtable.h>
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#include <asm/smp.h>
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#include <asm/elf.h>
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#include <asm/machdep.h>
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#include <asm/paca.h>
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#include <asm/time.h>
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#include <asm/cputable.h>
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#include <asm/sections.h>
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#include <asm/btext.h>
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#include <asm/nvram.h>
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#include <asm/setup.h>
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#include <asm/system.h>
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#include <asm/rtas.h>
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#include <asm/iommu.h>
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#include <asm/serial.h>
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#include <asm/cache.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/firmware.h>
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#include <asm/xmon.h>
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#include <asm/udbg.h>
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#include <asm/kexec.h>
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#include <asm/mmu_context.h>
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#include <asm/code-patching.h>
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#include "setup.h"
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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int boot_cpuid = 0;
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int __initdata boot_cpu_count;
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u64 ppc64_pft_size;
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/* Pick defaults since we might want to patch instructions
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* before we've read this from the device tree.
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*/
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struct ppc64_caches ppc64_caches = {
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.dline_size = 0x40,
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.log_dline_size = 6,
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.iline_size = 0x40,
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.log_iline_size = 6
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};
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EXPORT_SYMBOL_GPL(ppc64_caches);
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/*
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* These are used in binfmt_elf.c to put aux entries on the stack
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* for each elf executable being started.
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*/
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int dcache_bsize;
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int icache_bsize;
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int ucache_bsize;
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#ifdef CONFIG_SMP
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static char *smt_enabled_cmdline;
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/* Look for ibm,smt-enabled OF option */
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static void check_smt_enabled(void)
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{
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struct device_node *dn;
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const char *smt_option;
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/* Default to enabling all threads */
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smt_enabled_at_boot = threads_per_core;
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/* Allow the command line to overrule the OF option */
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if (smt_enabled_cmdline) {
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if (!strcmp(smt_enabled_cmdline, "on"))
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smt_enabled_at_boot = threads_per_core;
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else if (!strcmp(smt_enabled_cmdline, "off"))
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smt_enabled_at_boot = 0;
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else {
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long smt;
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int rc;
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rc = strict_strtol(smt_enabled_cmdline, 10, &smt);
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if (!rc)
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smt_enabled_at_boot =
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min(threads_per_core, (int)smt);
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}
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} else {
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dn = of_find_node_by_path("/options");
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if (dn) {
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smt_option = of_get_property(dn, "ibm,smt-enabled",
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NULL);
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if (smt_option) {
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if (!strcmp(smt_option, "on"))
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smt_enabled_at_boot = threads_per_core;
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else if (!strcmp(smt_option, "off"))
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smt_enabled_at_boot = 0;
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}
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of_node_put(dn);
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}
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}
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}
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/* Look for smt-enabled= cmdline option */
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static int __init early_smt_enabled(char *p)
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{
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smt_enabled_cmdline = p;
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return 0;
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}
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early_param("smt-enabled", early_smt_enabled);
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#else
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#define check_smt_enabled()
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#endif /* CONFIG_SMP */
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/*
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* Early initialization entry point. This is called by head.S
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* with MMU translation disabled. We rely on the "feature" of
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* the CPU that ignores the top 2 bits of the address in real
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* mode so we can access kernel globals normally provided we
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* only toy with things in the RMO region. From here, we do
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* some early parsing of the device-tree to setup out MEMBLOCK
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* data structures, and allocate & initialize the hash table
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* and segment tables so we can start running with translation
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* enabled.
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*
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* It is this function which will call the probe() callback of
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* the various platform types and copy the matching one to the
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* global ppc_md structure. Your platform can eventually do
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* some very early initializations from the probe() routine, but
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* this is not recommended, be very careful as, for example, the
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* device-tree is not accessible via normal means at this point.
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*/
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void __init early_setup(unsigned long dt_ptr)
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{
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/* -------- printk is _NOT_ safe to use here ! ------- */
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/* Identify CPU type */
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identify_cpu(0, mfspr(SPRN_PVR));
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/* Assume we're on cpu 0 for now. Don't write to the paca yet! */
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initialise_paca(&boot_paca, 0);
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setup_paca(&boot_paca);
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/* Initialize lockdep early or else spinlocks will blow */
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lockdep_init();
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/* -------- printk is now safe to use ------- */
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/* Enable early debugging if any specified (see udbg.h) */
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udbg_early_init();
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DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
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/*
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* Do early initialization using the flattened device
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* tree, such as retrieving the physical memory map or
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* calculating/retrieving the hash table size.
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*/
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early_init_devtree(__va(dt_ptr));
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/* Now we know the logical id of our boot cpu, setup the paca. */
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setup_paca(&paca[boot_cpuid]);
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/* Fix up paca fields required for the boot cpu */
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get_paca()->cpu_start = 1;
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/* Probe the machine type */
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probe_machine();
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setup_kdump_trampoline();
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DBG("Found, Initializing memory management...\n");
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/* Initialize the hash table or TLB handling */
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early_init_mmu();
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DBG(" <- early_setup()\n");
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}
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#ifdef CONFIG_SMP
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void early_setup_secondary(void)
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{
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/* Mark interrupts enabled in PACA */
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get_paca()->soft_enabled = 0;
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/* Initialize the hash table or TLB handling */
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early_init_mmu_secondary();
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}
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#endif /* CONFIG_SMP */
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#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
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void smp_release_cpus(void)
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{
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unsigned long *ptr;
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int i;
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DBG(" -> smp_release_cpus()\n");
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/* All secondary cpus are spinning on a common spinloop, release them
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* all now so they can start to spin on their individual paca
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* spinloops. For non SMP kernels, the secondary cpus never get out
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* of the common spinloop.
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*/
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ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
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- PHYSICAL_START);
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*ptr = __pa(generic_secondary_smp_init);
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/* And wait a bit for them to catch up */
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for (i = 0; i < 100000; i++) {
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mb();
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HMT_low();
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if (boot_cpu_count == 0)
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break;
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udelay(1);
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}
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DBG("boot_cpu_count = %d\n", boot_cpu_count);
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DBG(" <- smp_release_cpus()\n");
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}
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#endif /* CONFIG_SMP || CONFIG_KEXEC */
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/*
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* Initialize some remaining members of the ppc64_caches and systemcfg
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* structures
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* (at least until we get rid of them completely). This is mostly some
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* cache informations about the CPU that will be used by cache flush
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* routines and/or provided to userland
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*/
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static void __init initialize_cache_info(void)
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{
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struct device_node *np;
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unsigned long num_cpus = 0;
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DBG(" -> initialize_cache_info()\n");
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for (np = NULL; (np = of_find_node_by_type(np, "cpu"));) {
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num_cpus += 1;
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/* We're assuming *all* of the CPUs have the same
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* d-cache and i-cache sizes... -Peter
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*/
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if ( num_cpus == 1 ) {
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const u32 *sizep, *lsizep;
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u32 size, lsize;
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size = 0;
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lsize = cur_cpu_spec->dcache_bsize;
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sizep = of_get_property(np, "d-cache-size", NULL);
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if (sizep != NULL)
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size = *sizep;
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lsizep = of_get_property(np, "d-cache-block-size", NULL);
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/* fallback if block size missing */
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if (lsizep == NULL)
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lsizep = of_get_property(np, "d-cache-line-size", NULL);
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if (lsizep != NULL)
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lsize = *lsizep;
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if (sizep == 0 || lsizep == 0)
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DBG("Argh, can't find dcache properties ! "
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"sizep: %p, lsizep: %p\n", sizep, lsizep);
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ppc64_caches.dsize = size;
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ppc64_caches.dline_size = lsize;
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ppc64_caches.log_dline_size = __ilog2(lsize);
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ppc64_caches.dlines_per_page = PAGE_SIZE / lsize;
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size = 0;
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lsize = cur_cpu_spec->icache_bsize;
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sizep = of_get_property(np, "i-cache-size", NULL);
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if (sizep != NULL)
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size = *sizep;
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lsizep = of_get_property(np, "i-cache-block-size", NULL);
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if (lsizep == NULL)
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lsizep = of_get_property(np, "i-cache-line-size", NULL);
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if (lsizep != NULL)
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lsize = *lsizep;
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if (sizep == 0 || lsizep == 0)
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DBG("Argh, can't find icache properties ! "
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"sizep: %p, lsizep: %p\n", sizep, lsizep);
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ppc64_caches.isize = size;
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ppc64_caches.iline_size = lsize;
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ppc64_caches.log_iline_size = __ilog2(lsize);
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ppc64_caches.ilines_per_page = PAGE_SIZE / lsize;
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}
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}
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DBG(" <- initialize_cache_info()\n");
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}
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/*
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* Do some initial setup of the system. The parameters are those which
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* were passed in from the bootloader.
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*/
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void __init setup_system(void)
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{
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DBG(" -> setup_system()\n");
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/* Apply the CPUs-specific and firmware specific fixups to kernel
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* text (nop out sections not relevant to this CPU or this firmware)
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*/
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do_feature_fixups(cur_cpu_spec->cpu_features,
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&__start___ftr_fixup, &__stop___ftr_fixup);
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do_feature_fixups(cur_cpu_spec->mmu_features,
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&__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup);
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do_feature_fixups(powerpc_firmware_features,
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&__start___fw_ftr_fixup, &__stop___fw_ftr_fixup);
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do_lwsync_fixups(cur_cpu_spec->cpu_features,
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&__start___lwsync_fixup, &__stop___lwsync_fixup);
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/*
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* Unflatten the device-tree passed by prom_init or kexec
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*/
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unflatten_device_tree();
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/*
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* Fill the ppc64_caches & systemcfg structures with informations
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* retrieved from the device-tree.
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*/
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initialize_cache_info();
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#ifdef CONFIG_PPC_RTAS
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/*
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* Initialize RTAS if available
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*/
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rtas_initialize();
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#endif /* CONFIG_PPC_RTAS */
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/*
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* Check if we have an initrd provided via the device-tree
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*/
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check_for_initrd();
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/*
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* Do some platform specific early initializations, that includes
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* setting up the hash table pointers. It also sets up some interrupt-mapping
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* related options that will be used by finish_device_tree()
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*/
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if (ppc_md.init_early)
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ppc_md.init_early();
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/*
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* We can discover serial ports now since the above did setup the
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* hash table management for us, thus ioremap works. We do that early
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* so that further code can be debugged
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*/
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find_legacy_serial_ports();
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/*
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* Register early console
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*/
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register_early_udbg_console();
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/*
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* Initialize xmon
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*/
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xmon_setup();
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smp_setup_cpu_maps();
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check_smt_enabled();
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#ifdef CONFIG_SMP
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/* Release secondary cpus out of their spinloops at 0x60 now that
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* we can map physical -> logical CPU ids
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*/
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smp_release_cpus();
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#endif
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printk("Starting Linux PPC64 %s\n", init_utsname()->version);
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printk("-----------------------------------------------------\n");
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printk("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
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printk("physicalMemorySize = 0x%llx\n", memblock_phys_mem_size());
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if (ppc64_caches.dline_size != 0x80)
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printk("ppc64_caches.dcache_line_size = 0x%x\n",
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ppc64_caches.dline_size);
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if (ppc64_caches.iline_size != 0x80)
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printk("ppc64_caches.icache_line_size = 0x%x\n",
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ppc64_caches.iline_size);
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#ifdef CONFIG_PPC_STD_MMU_64
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if (htab_address)
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printk("htab_address = 0x%p\n", htab_address);
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printk("htab_hash_mask = 0x%lx\n", htab_hash_mask);
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#endif /* CONFIG_PPC_STD_MMU_64 */
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if (PHYSICAL_START > 0)
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printk("physical_start = 0x%llx\n",
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(unsigned long long)PHYSICAL_START);
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printk("-----------------------------------------------------\n");
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DBG(" <- setup_system()\n");
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}
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/* This returns the limit below which memory accesses to the linear
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* mapping are guarnateed not to cause a TLB or SLB miss. This is
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* used to allocate interrupt or emergency stacks for which our
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* exception entry path doesn't deal with being interrupted.
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*/
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static u64 safe_stack_limit(void)
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{
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#ifdef CONFIG_PPC_BOOK3E
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/* Freescale BookE bolts the entire linear mapping */
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if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
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return linear_map_top;
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/* Other BookE, we assume the first GB is bolted */
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return 1ul << 30;
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#else
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/* BookS, the first segment is bolted */
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if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
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return 1UL << SID_SHIFT_1T;
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return 1UL << SID_SHIFT;
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#endif
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}
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static void __init irqstack_early_init(void)
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{
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u64 limit = safe_stack_limit();
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unsigned int i;
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/*
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* Interrupt stacks must be in the first segment since we
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* cannot afford to take SLB misses on them.
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*/
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for_each_possible_cpu(i) {
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softirq_ctx[i] = (struct thread_info *)
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__va(memblock_alloc_base(THREAD_SIZE,
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THREAD_SIZE, limit));
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hardirq_ctx[i] = (struct thread_info *)
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__va(memblock_alloc_base(THREAD_SIZE,
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THREAD_SIZE, limit));
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}
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}
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#ifdef CONFIG_PPC_BOOK3E
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static void __init exc_lvl_early_init(void)
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{
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extern unsigned int interrupt_base_book3e;
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extern unsigned int exc_debug_debug_book3e;
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unsigned int i;
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for_each_possible_cpu(i) {
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critirq_ctx[i] = (struct thread_info *)
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__va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
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dbgirq_ctx[i] = (struct thread_info *)
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__va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
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mcheckirq_ctx[i] = (struct thread_info *)
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__va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
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}
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if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
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patch_branch(&interrupt_base_book3e + (0x040 / 4) + 1,
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(unsigned long)&exc_debug_debug_book3e, 0);
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}
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#else
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#define exc_lvl_early_init()
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#endif
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/*
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* Stack space used when we detect a bad kernel stack pointer, and
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* early in SMP boots before relocation is enabled.
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*/
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static void __init emergency_stack_init(void)
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{
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u64 limit;
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unsigned int i;
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/*
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* Emergency stacks must be under 256MB, we cannot afford to take
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|
* SLB misses on them. The ABI also requires them to be 128-byte
|
|
* aligned.
|
|
*
|
|
* Since we use these as temporary stacks during secondary CPU
|
|
* bringup, we need to get at them in real mode. This means they
|
|
* must also be within the RMO region.
|
|
*/
|
|
limit = min(safe_stack_limit(), ppc64_rma_size);
|
|
|
|
for_each_possible_cpu(i) {
|
|
unsigned long sp;
|
|
sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
|
|
sp += THREAD_SIZE;
|
|
paca[i].emergency_sp = __va(sp);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Called into from start_kernel this initializes bootmem, which is used
|
|
* to manage page allocation until mem_init is called.
|
|
*/
|
|
void __init setup_arch(char **cmdline_p)
|
|
{
|
|
ppc64_boot_msg(0x12, "Setup Arch");
|
|
|
|
*cmdline_p = cmd_line;
|
|
|
|
/*
|
|
* Set cache line size based on type of cpu as a default.
|
|
* Systems with OF can look in the properties on the cpu node(s)
|
|
* for a possibly more accurate value.
|
|
*/
|
|
dcache_bsize = ppc64_caches.dline_size;
|
|
icache_bsize = ppc64_caches.iline_size;
|
|
|
|
/* reboot on panic */
|
|
panic_timeout = 180;
|
|
|
|
if (ppc_md.panic)
|
|
setup_panic();
|
|
|
|
init_mm.start_code = (unsigned long)_stext;
|
|
init_mm.end_code = (unsigned long) _etext;
|
|
init_mm.end_data = (unsigned long) _edata;
|
|
init_mm.brk = klimit;
|
|
|
|
irqstack_early_init();
|
|
exc_lvl_early_init();
|
|
emergency_stack_init();
|
|
|
|
#ifdef CONFIG_PPC_STD_MMU_64
|
|
stabs_alloc();
|
|
#endif
|
|
/* set up the bootmem stuff with available memory */
|
|
do_init_bootmem();
|
|
sparse_init();
|
|
|
|
#ifdef CONFIG_DUMMY_CONSOLE
|
|
conswitchp = &dummy_con;
|
|
#endif
|
|
|
|
if (ppc_md.setup_arch)
|
|
ppc_md.setup_arch();
|
|
|
|
paging_init();
|
|
|
|
/* Initialize the MMU context management stuff */
|
|
mmu_context_init();
|
|
|
|
ppc64_boot_msg(0x15, "Setup Done");
|
|
}
|
|
|
|
|
|
/* ToDo: do something useful if ppc_md is not yet setup. */
|
|
#define PPC64_LINUX_FUNCTION 0x0f000000
|
|
#define PPC64_IPL_MESSAGE 0xc0000000
|
|
#define PPC64_TERM_MESSAGE 0xb0000000
|
|
|
|
static void ppc64_do_msg(unsigned int src, const char *msg)
|
|
{
|
|
if (ppc_md.progress) {
|
|
char buf[128];
|
|
|
|
sprintf(buf, "%08X\n", src);
|
|
ppc_md.progress(buf, 0);
|
|
snprintf(buf, 128, "%s", msg);
|
|
ppc_md.progress(buf, 0);
|
|
}
|
|
}
|
|
|
|
/* Print a boot progress message. */
|
|
void ppc64_boot_msg(unsigned int src, const char *msg)
|
|
{
|
|
ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_IPL_MESSAGE|src, msg);
|
|
printk("[boot]%04x %s\n", src, msg);
|
|
}
|
|
|
|
#ifdef CONFIG_SMP
|
|
#define PCPU_DYN_SIZE ()
|
|
|
|
static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
|
|
{
|
|
return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align,
|
|
__pa(MAX_DMA_ADDRESS));
|
|
}
|
|
|
|
static void __init pcpu_fc_free(void *ptr, size_t size)
|
|
{
|
|
free_bootmem(__pa(ptr), size);
|
|
}
|
|
|
|
static int pcpu_cpu_distance(unsigned int from, unsigned int to)
|
|
{
|
|
if (cpu_to_node(from) == cpu_to_node(to))
|
|
return LOCAL_DISTANCE;
|
|
else
|
|
return REMOTE_DISTANCE;
|
|
}
|
|
|
|
unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
|
|
EXPORT_SYMBOL(__per_cpu_offset);
|
|
|
|
void __init setup_per_cpu_areas(void)
|
|
{
|
|
const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
|
|
size_t atom_size;
|
|
unsigned long delta;
|
|
unsigned int cpu;
|
|
int rc;
|
|
|
|
/*
|
|
* Linear mapping is one of 4K, 1M and 16M. For 4K, no need
|
|
* to group units. For larger mappings, use 1M atom which
|
|
* should be large enough to contain a number of units.
|
|
*/
|
|
if (mmu_linear_psize == MMU_PAGE_4K)
|
|
atom_size = PAGE_SIZE;
|
|
else
|
|
atom_size = 1 << 20;
|
|
|
|
rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
|
|
pcpu_fc_alloc, pcpu_fc_free);
|
|
if (rc < 0)
|
|
panic("cannot initialize percpu area (err=%d)", rc);
|
|
|
|
delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
|
|
for_each_possible_cpu(cpu) {
|
|
__per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
|
|
paca[cpu].data_offset = __per_cpu_offset[cpu];
|
|
}
|
|
}
|
|
#endif
|
|
|
|
|
|
#ifdef CONFIG_PPC_INDIRECT_IO
|
|
struct ppc_pci_io ppc_pci_io;
|
|
EXPORT_SYMBOL(ppc_pci_io);
|
|
#endif /* CONFIG_PPC_INDIRECT_IO */
|
|
|