39a90865f0
This copies the pci_config_lock idea from x86 over, allowing us to kill off a couple of existing private locks. At the same time, these need to be converted to raw spinlocks for -rt kernels, so we make that change at the same time. This should make it easier for future parts to get the locking right instead of inevitable ending up with lock type mismatches. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
171 lines
4.7 KiB
C
171 lines
4.7 KiB
C
/*
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* Generic SH7786 PCI-Express operations.
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*
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* Copyright (C) 2009 - 2010 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License v2. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include "pcie-sh7786.h"
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enum {
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PCI_ACCESS_READ,
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PCI_ACCESS_WRITE,
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};
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static int sh7786_pcie_config_access(unsigned char access_type,
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struct pci_bus *bus, unsigned int devfn, int where, u32 *data)
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{
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struct pci_channel *chan = bus->sysdata;
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int dev, func, type, reg;
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dev = PCI_SLOT(devfn);
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func = PCI_FUNC(devfn);
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type = !!bus->parent;
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reg = where & ~3;
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if (bus->number > 255 || dev > 31 || func > 7)
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return PCIBIOS_FUNC_NOT_SUPPORTED;
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/*
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* While each channel has its own memory-mapped extended config
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* space, it's generally only accessible when in endpoint mode.
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* When in root complex mode, the controller is unable to target
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* itself with either type 0 or type 1 accesses, and indeed, any
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* controller initiated target transfer to its own config space
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* result in a completer abort.
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*
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* Each channel effectively only supports a single device, but as
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* the same channel <-> device access works for any PCI_SLOT()
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* value, we cheat a bit here and bind the controller's config
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* space to devfn 0 in order to enable self-enumeration. In this
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* case the regular PAR/PDR path is sidelined and the mangled
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* config access itself is initiated as a SuperHyway transaction.
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*/
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if (pci_is_root_bus(bus)) {
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if (dev == 0) {
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if (access_type == PCI_ACCESS_READ)
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*data = pci_read_reg(chan, PCI_REG(reg));
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else
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pci_write_reg(chan, *data, PCI_REG(reg));
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return PCIBIOS_SUCCESSFUL;
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} else if (dev > 1)
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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/* Clear errors */
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pci_write_reg(chan, pci_read_reg(chan, SH4A_PCIEERRFR), SH4A_PCIEERRFR);
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/* Set the PIO address */
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pci_write_reg(chan, (bus->number << 24) | (dev << 19) |
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(func << 16) | reg, SH4A_PCIEPAR);
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/* Enable the configuration access */
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pci_write_reg(chan, (1 << 31) | (type << 8), SH4A_PCIEPCTLR);
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/* Check for errors */
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if (pci_read_reg(chan, SH4A_PCIEERRFR) & 0x10)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* Check for master and target aborts */
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if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28)))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (access_type == PCI_ACCESS_READ)
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*data = pci_read_reg(chan, SH4A_PCIEPDR);
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else
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pci_write_reg(chan, *data, SH4A_PCIEPDR);
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/* Disable the configuration access */
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pci_write_reg(chan, 0, SH4A_PCIEPCTLR);
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return PCIBIOS_SUCCESSFUL;
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}
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static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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unsigned long flags;
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int ret;
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u32 data;
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if ((size == 2) && (where & 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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else if ((size == 4) && (where & 3))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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raw_spin_lock_irqsave(&pci_config_lock, flags);
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ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
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devfn, where, &data);
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if (ret != PCIBIOS_SUCCESSFUL) {
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*val = 0xffffffff;
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goto out;
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}
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if (size == 1)
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*val = (data >> ((where & 3) << 3)) & 0xff;
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else if (size == 2)
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*val = (data >> ((where & 2) << 3)) & 0xffff;
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else
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*val = data;
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dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x "
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"where=0x%04x size=%d val=0x%08lx\n", bus->number,
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devfn, where, size, (unsigned long)*val);
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out:
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raw_spin_unlock_irqrestore(&pci_config_lock, flags);
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return ret;
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}
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static int sh7786_pcie_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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unsigned long flags;
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int shift, ret;
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u32 data;
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if ((size == 2) && (where & 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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else if ((size == 4) && (where & 3))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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raw_spin_lock_irqsave(&pci_config_lock, flags);
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ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
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devfn, where, &data);
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if (ret != PCIBIOS_SUCCESSFUL)
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goto out;
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dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x "
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"where=0x%04x size=%d val=%08lx\n", bus->number,
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devfn, where, size, (unsigned long)val);
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if (size == 1) {
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shift = (where & 3) << 3;
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data &= ~(0xff << shift);
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data |= ((val & 0xff) << shift);
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} else if (size == 2) {
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shift = (where & 2) << 3;
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data &= ~(0xffff << shift);
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data |= ((val & 0xffff) << shift);
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} else
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data = val;
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ret = sh7786_pcie_config_access(PCI_ACCESS_WRITE, bus,
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devfn, where, &data);
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out:
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raw_spin_unlock_irqrestore(&pci_config_lock, flags);
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return ret;
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}
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struct pci_ops sh7786_pci_ops = {
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.read = sh7786_pcie_read,
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.write = sh7786_pcie_write,
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};
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