86f5362e7a
The commit d0a0ce3e77 ("thermal: exynos: Add
missing definations and code cleanup") has removed setting of test MUX address
value at TMU configuration setting.
This field is not present on Exynos4210 and Exynos5 SoCs. However on Exynos4412
SoC it is required to set this field after reset because without it TMU shows
maximal available temperature, which causes immediate platform shutdown.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
316 lines
11 KiB
C
316 lines
11 KiB
C
/*
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* exynos_tmu.h - Samsung EXYNOS TMU (Thermal Management Unit)
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*
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* Copyright (C) 2011 Samsung Electronics
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* Donggeun Kim <dg77.kim@samsung.com>
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* Amit Daniel Kachhap <amit.daniel@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _EXYNOS_TMU_H
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#define _EXYNOS_TMU_H
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#include <linux/cpu_cooling.h>
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#include "exynos_thermal_common.h"
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enum calibration_type {
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TYPE_ONE_POINT_TRIMMING,
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TYPE_ONE_POINT_TRIMMING_25,
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TYPE_ONE_POINT_TRIMMING_85,
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TYPE_TWO_POINT_TRIMMING,
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TYPE_NONE,
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};
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enum calibration_mode {
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SW_MODE,
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HW_MODE,
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};
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enum soc_type {
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SOC_ARCH_EXYNOS4210 = 1,
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SOC_ARCH_EXYNOS4412,
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SOC_ARCH_EXYNOS5250,
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SOC_ARCH_EXYNOS5440,
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};
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/**
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* EXYNOS TMU supported features.
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* TMU_SUPPORT_EMULATION - This features is used to set user defined
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* temperature to the TMU controller.
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* TMU_SUPPORT_MULTI_INST - This features denotes that the soc
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* has many instances of TMU.
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* TMU_SUPPORT_TRIM_RELOAD - This features shows that trimming can
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* be reloaded.
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* TMU_SUPPORT_FALLING_TRIP - This features shows that interrupt can
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* be registered for falling trips also.
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* TMU_SUPPORT_READY_STATUS - This feature tells that the TMU current
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* state(active/idle) can be checked.
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* TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
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* sample time.
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* TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
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* sensors shares some common registers.
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* TMU_SUPPORT - macro to compare the above features with the supplied.
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*/
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#define TMU_SUPPORT_EMULATION BIT(0)
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#define TMU_SUPPORT_MULTI_INST BIT(1)
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#define TMU_SUPPORT_TRIM_RELOAD BIT(2)
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#define TMU_SUPPORT_FALLING_TRIP BIT(3)
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#define TMU_SUPPORT_READY_STATUS BIT(4)
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#define TMU_SUPPORT_EMUL_TIME BIT(5)
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#define TMU_SUPPORT_SHARED_MEMORY BIT(6)
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#define TMU_SUPPORTS(a, b) (a->features & TMU_SUPPORT_ ## b)
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/**
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* struct exynos_tmu_register - register descriptors to access registers and
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* bitfields. The register validity, offsets and bitfield values may vary
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* slightly across different exynos SOC's.
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* @triminfo_data: register containing 2 pont trimming data
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* @triminfo_25_shift: shift bit of the 25 C trim value in triminfo_data reg.
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* @triminfo_85_shift: shift bit of the 85 C trim value in triminfo_data reg.
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* @triminfo_ctrl: trim info controller register.
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* @triminfo_reload_shift: shift of triminfo reload enable bit in triminfo_ctrl
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reg.
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* @tmu_ctrl: TMU main controller register.
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* @test_mux_addr_shift: shift bits of test mux address.
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* @buf_vref_sel_shift: shift bits of reference voltage in tmu_ctrl register.
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* @buf_vref_sel_mask: mask bits of reference voltage in tmu_ctrl register.
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* @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register.
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* @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register.
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* @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register.
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* @buf_slope_sel_shift: shift bits of amplifier gain value in tmu_ctrl
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register.
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* @buf_slope_sel_mask: mask bits of amplifier gain value in tmu_ctrl register.
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* @calib_mode_shift: shift bits of calibration mode value in tmu_ctrl
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register.
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* @calib_mode_mask: mask bits of calibration mode value in tmu_ctrl
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register.
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* @therm_trip_tq_en_shift: shift bits of thermal trip enable by TQ pin in
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tmu_ctrl register.
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* @core_en_shift: shift bits of TMU core enable bit in tmu_ctrl register.
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* @tmu_status: register drescribing the TMU status.
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* @tmu_cur_temp: register containing the current temperature of the TMU.
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* @tmu_cur_temp_shift: shift bits of current temp value in tmu_cur_temp
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register.
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* @threshold_temp: register containing the base threshold level.
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* @threshold_th0: Register containing first set of rising levels.
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* @threshold_th0_l0_shift: shift bits of level0 threshold temperature.
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* @threshold_th0_l1_shift: shift bits of level1 threshold temperature.
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* @threshold_th0_l2_shift: shift bits of level2 threshold temperature.
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* @threshold_th0_l3_shift: shift bits of level3 threshold temperature.
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* @threshold_th1: Register containing second set of rising levels.
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* @threshold_th1_l0_shift: shift bits of level0 threshold temperature.
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* @threshold_th1_l1_shift: shift bits of level1 threshold temperature.
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* @threshold_th1_l2_shift: shift bits of level2 threshold temperature.
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* @threshold_th1_l3_shift: shift bits of level3 threshold temperature.
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* @threshold_th2: Register containing third set of rising levels.
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* @threshold_th2_l0_shift: shift bits of level0 threshold temperature.
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* @threshold_th3: Register containing fourth set of rising levels.
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* @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
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* @tmu_inten: register containing the different threshold interrupt
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enable bits.
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* @inten_rise_shift: shift bits of all rising interrupt bits.
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* @inten_rise_mask: mask bits of all rising interrupt bits.
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* @inten_fall_shift: shift bits of all rising interrupt bits.
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* @inten_fall_mask: mask bits of all rising interrupt bits.
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* @inten_rise0_shift: shift bits of rising 0 interrupt bits.
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* @inten_rise1_shift: shift bits of rising 1 interrupt bits.
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* @inten_rise2_shift: shift bits of rising 2 interrupt bits.
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* @inten_rise3_shift: shift bits of rising 3 interrupt bits.
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* @inten_fall0_shift: shift bits of falling 0 interrupt bits.
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* @inten_fall1_shift: shift bits of falling 1 interrupt bits.
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* @inten_fall2_shift: shift bits of falling 2 interrupt bits.
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* @inten_fall3_shift: shift bits of falling 3 interrupt bits.
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* @tmu_intstat: Register containing the interrupt status values.
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* @tmu_intclear: Register for clearing the raised interrupt status.
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* @emul_con: TMU emulation controller register.
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* @emul_temp_shift: shift bits of emulation temperature.
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* @emul_time_shift: shift bits of emulation time.
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* @emul_time_mask: mask bits of emulation time.
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* @tmu_irqstatus: register to find which TMU generated interrupts.
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* @tmu_pmin: register to get/set the Pmin value.
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*/
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struct exynos_tmu_registers {
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u32 triminfo_data;
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u32 triminfo_25_shift;
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u32 triminfo_85_shift;
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u32 triminfo_ctrl;
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u32 triminfo_reload_shift;
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u32 tmu_ctrl;
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u32 test_mux_addr_shift;
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u32 buf_vref_sel_shift;
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u32 buf_vref_sel_mask;
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u32 therm_trip_mode_shift;
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u32 therm_trip_mode_mask;
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u32 therm_trip_en_shift;
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u32 buf_slope_sel_shift;
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u32 buf_slope_sel_mask;
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u32 calib_mode_shift;
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u32 calib_mode_mask;
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u32 therm_trip_tq_en_shift;
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u32 core_en_shift;
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u32 tmu_status;
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u32 tmu_cur_temp;
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u32 tmu_cur_temp_shift;
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u32 threshold_temp;
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u32 threshold_th0;
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u32 threshold_th0_l0_shift;
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u32 threshold_th0_l1_shift;
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u32 threshold_th0_l2_shift;
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u32 threshold_th0_l3_shift;
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u32 threshold_th1;
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u32 threshold_th1_l0_shift;
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u32 threshold_th1_l1_shift;
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u32 threshold_th1_l2_shift;
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u32 threshold_th1_l3_shift;
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u32 threshold_th2;
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u32 threshold_th2_l0_shift;
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u32 threshold_th3;
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u32 threshold_th3_l0_shift;
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u32 tmu_inten;
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u32 inten_rise_shift;
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u32 inten_rise_mask;
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u32 inten_fall_shift;
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u32 inten_fall_mask;
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u32 inten_rise0_shift;
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u32 inten_rise1_shift;
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u32 inten_rise2_shift;
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u32 inten_rise3_shift;
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u32 inten_fall0_shift;
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u32 inten_fall1_shift;
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u32 inten_fall2_shift;
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u32 inten_fall3_shift;
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u32 tmu_intstat;
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u32 tmu_intclear;
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u32 emul_con;
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u32 emul_temp_shift;
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u32 emul_time_shift;
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u32 emul_time_mask;
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u32 tmu_irqstatus;
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u32 tmu_pmin;
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};
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/**
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* struct exynos_tmu_platform_data
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* @threshold: basic temperature for generating interrupt
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* 25 <= threshold <= 125 [unit: degree Celsius]
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* @threshold_falling: differntial value for setting threshold
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* of temperature falling interrupt.
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* @trigger_levels: array for each interrupt levels
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* [unit: degree Celsius]
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* 0: temperature for trigger_level0 interrupt
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* condition for trigger_level0 interrupt:
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* current temperature > threshold + trigger_levels[0]
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* 1: temperature for trigger_level1 interrupt
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* condition for trigger_level1 interrupt:
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* current temperature > threshold + trigger_levels[1]
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* 2: temperature for trigger_level2 interrupt
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* condition for trigger_level2 interrupt:
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* current temperature > threshold + trigger_levels[2]
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* 3: temperature for trigger_level3 interrupt
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* condition for trigger_level3 interrupt:
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* current temperature > threshold + trigger_levels[3]
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* @trigger_type: defines the type of trigger. Possible values are,
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* THROTTLE_ACTIVE trigger type
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* THROTTLE_PASSIVE trigger type
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* SW_TRIP trigger type
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* HW_TRIP
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* @trigger_enable[]: array to denote which trigger levels are enabled.
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* 1 = enable trigger_level[] interrupt,
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* 0 = disable trigger_level[] interrupt
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* @max_trigger_level: max trigger level supported by the TMU
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* @gain: gain of amplifier in the positive-TC generator block
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* 0 <= gain <= 15
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* @reference_voltage: reference voltage of amplifier
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* in the positive-TC generator block
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* 0 <= reference_voltage <= 31
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* @noise_cancel_mode: noise cancellation mode
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* 000, 100, 101, 110 and 111 can be different modes
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* @type: determines the type of SOC
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* @efuse_value: platform defined fuse value
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* @min_efuse_value: minimum valid trimming data
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* @max_efuse_value: maximum valid trimming data
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* @first_point_trim: temp value of the first point trimming
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* @second_point_trim: temp value of the second point trimming
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* @default_temp_offset: default temperature offset in case of no trimming
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* @test_mux; information if SoC supports test MUX
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* @cal_type: calibration type for temperature
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* @cal_mode: calibration mode for temperature
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* @freq_clip_table: Table representing frequency reduction percentage.
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* @freq_tab_count: Count of the above table as frequency reduction may
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* applicable to only some of the trigger levels.
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* @registers: Pointer to structure containing all the TMU controller registers
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* and bitfields shifts and masks.
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* @features: a bitfield value indicating the features supported in SOC like
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* emulation, multi instance etc
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*
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* This structure is required for configuration of exynos_tmu driver.
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*/
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struct exynos_tmu_platform_data {
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u8 threshold;
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u8 threshold_falling;
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u8 trigger_levels[MAX_TRIP_COUNT];
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enum trigger_type trigger_type[MAX_TRIP_COUNT];
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bool trigger_enable[MAX_TRIP_COUNT];
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u8 max_trigger_level;
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u8 gain;
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u8 reference_voltage;
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u8 noise_cancel_mode;
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u32 efuse_value;
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u32 min_efuse_value;
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u32 max_efuse_value;
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u8 first_point_trim;
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u8 second_point_trim;
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u8 default_temp_offset;
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u8 test_mux;
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enum calibration_type cal_type;
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enum calibration_mode cal_mode;
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enum soc_type type;
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struct freq_clip_table freq_tab[4];
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unsigned int freq_tab_count;
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const struct exynos_tmu_registers *registers;
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unsigned int features;
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};
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/**
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* struct exynos_tmu_init_data
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* @tmu_count: number of TMU instances.
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* @tmu_data: platform data of all TMU instances.
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* This structure is required to store data for multi-instance exynos tmu
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* driver.
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*/
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struct exynos_tmu_init_data {
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int tmu_count;
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struct exynos_tmu_platform_data tmu_data[];
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};
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#endif /* _EXYNOS_TMU_H */
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