5f97f7f940
This adds support for the Atmel AVR32 architecture as well as the AT32AP7000 CPU and the AT32STK1000 development board. AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code density. The AVR32 architecture is not binary compatible with earlier 8-bit AVR architectures. The AVR32 architecture, including the instruction set, is described by the AVR32 Architecture Manual, available from http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It features a 7-stage pipeline, 16KB instruction and data caches and a full Memory Management Unit. It also comes with a large set of integrated peripherals, many of which are shared with the AT91 ARM-based controllers from Atmel. Full data sheet is available from http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf while the CPU core implementation including caches and MMU is documented by the AVR32 AP Technical Reference, available from http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf Information about the AT32STK1000 development board can be found at http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918 including a BSP CD image with an earlier version of this patch, development tools (binaries and source/patches) and a root filesystem image suitable for booting from SD card. Alternatively, there's a preliminary "getting started" guide available at http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links to the sources and patches you will need in order to set up a cross-compiling environment for avr32-linux. This patch, as well as the other patches included with the BSP and the toolchain patches, is actively supported by Atmel Corporation. [dmccr@us.ibm.com: Fix more pxx_page macro locations] [bunk@stusta.de: fix `make defconfig'] Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Dave McCracken <dmccr@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
296 lines
7 KiB
C
296 lines
7 KiB
C
/*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_AVR32_BITOPS_H
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#define __ASM_AVR32_BITOPS_H
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#include <asm/byteorder.h>
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#include <asm/system.h>
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/*
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* clear_bit() doesn't provide any barrier for the compiler
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*/
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#define smp_mb__before_clear_bit() barrier()
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#define smp_mb__after_clear_bit() barrier()
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/*
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered. See __set_bit()
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* if you do not require the atomic guarantees.
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*
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void set_bit(int nr, volatile void * addr)
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{
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unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
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unsigned long tmp;
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if (__builtin_constant_p(nr)) {
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asm volatile(
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"1: ssrf 5\n"
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" ld.w %0, %2\n"
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" sbr %0, %3\n"
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" stcond %1, %0\n"
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" brne 1b"
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: "=&r"(tmp), "=o"(*p)
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: "m"(*p), "i"(nr)
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: "cc");
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} else {
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unsigned long mask = 1UL << (nr % BITS_PER_LONG);
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asm volatile(
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"1: ssrf 5\n"
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" ld.w %0, %2\n"
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" or %0, %3\n"
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" stcond %1, %0\n"
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" brne 1b"
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: "=&r"(tmp), "=o"(*p)
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: "m"(*p), "r"(mask)
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: "cc");
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}
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}
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/*
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* clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit() is atomic and may not be reordered. However, it does
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* not contain a memory barrier, so if it is used for locking purposes,
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
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* in order to ensure changes are visible on other processors.
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*/
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static inline void clear_bit(int nr, volatile void * addr)
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{
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unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
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unsigned long tmp;
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if (__builtin_constant_p(nr)) {
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asm volatile(
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"1: ssrf 5\n"
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" ld.w %0, %2\n"
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" cbr %0, %3\n"
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" stcond %1, %0\n"
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" brne 1b"
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: "=&r"(tmp), "=o"(*p)
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: "m"(*p), "i"(nr)
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: "cc");
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} else {
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unsigned long mask = 1UL << (nr % BITS_PER_LONG);
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asm volatile(
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"1: ssrf 5\n"
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" ld.w %0, %2\n"
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" andn %0, %3\n"
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" stcond %1, %0\n"
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" brne 1b"
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: "=&r"(tmp), "=o"(*p)
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: "m"(*p), "r"(mask)
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: "cc");
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}
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}
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/*
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* change_bit - Toggle a bit in memory
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* @nr: Bit to change
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* @addr: Address to start counting from
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*
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* change_bit() is atomic and may not be reordered.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void change_bit(int nr, volatile void * addr)
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{
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unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
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unsigned long mask = 1UL << (nr % BITS_PER_LONG);
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unsigned long tmp;
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asm volatile(
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"1: ssrf 5\n"
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" ld.w %0, %2\n"
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" eor %0, %3\n"
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" stcond %1, %0\n"
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" brne 1b"
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: "=&r"(tmp), "=o"(*p)
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: "m"(*p), "r"(mask)
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: "cc");
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}
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/*
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* test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_set_bit(int nr, volatile void * addr)
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{
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unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
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unsigned long mask = 1UL << (nr % BITS_PER_LONG);
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unsigned long tmp, old;
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if (__builtin_constant_p(nr)) {
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asm volatile(
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"1: ssrf 5\n"
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" ld.w %0, %3\n"
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" mov %2, %0\n"
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" sbr %0, %4\n"
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" stcond %1, %0\n"
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" brne 1b"
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: "=&r"(tmp), "=o"(*p), "=&r"(old)
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: "m"(*p), "i"(nr)
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: "memory", "cc");
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} else {
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asm volatile(
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"1: ssrf 5\n"
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" ld.w %2, %3\n"
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" or %0, %2, %4\n"
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" stcond %1, %0\n"
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" brne 1b"
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: "=&r"(tmp), "=o"(*p), "=&r"(old)
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: "m"(*p), "r"(mask)
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: "memory", "cc");
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}
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return (old & mask) != 0;
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}
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/*
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_clear_bit(int nr, volatile void * addr)
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{
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unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
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unsigned long mask = 1UL << (nr % BITS_PER_LONG);
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unsigned long tmp, old;
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if (__builtin_constant_p(nr)) {
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asm volatile(
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"1: ssrf 5\n"
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" ld.w %0, %3\n"
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" mov %2, %0\n"
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" cbr %0, %4\n"
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" stcond %1, %0\n"
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" brne 1b"
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: "=&r"(tmp), "=o"(*p), "=&r"(old)
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: "m"(*p), "i"(nr)
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: "memory", "cc");
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} else {
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asm volatile(
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"1: ssrf 5\n"
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" ld.w %0, %3\n"
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" mov %2, %0\n"
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" andn %0, %4\n"
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" stcond %1, %0\n"
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" brne 1b"
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: "=&r"(tmp), "=o"(*p), "=&r"(old)
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: "m"(*p), "r"(mask)
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: "memory", "cc");
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}
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return (old & mask) != 0;
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}
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/*
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* test_and_change_bit - Change a bit and return its old value
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* @nr: Bit to change
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_change_bit(int nr, volatile void * addr)
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{
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unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
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unsigned long mask = 1UL << (nr % BITS_PER_LONG);
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unsigned long tmp, old;
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asm volatile(
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"1: ssrf 5\n"
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" ld.w %2, %3\n"
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" eor %0, %2, %4\n"
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" stcond %1, %0\n"
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" brne 1b"
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: "=&r"(tmp), "=o"(*p), "=&r"(old)
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: "m"(*p), "r"(mask)
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: "memory", "cc");
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return (old & mask) != 0;
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}
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#include <asm-generic/bitops/non-atomic.h>
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/* Find First bit Set */
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static inline unsigned long __ffs(unsigned long word)
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{
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unsigned long result;
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asm("brev %1\n\t"
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"clz %0,%1"
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: "=r"(result), "=&r"(word)
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: "1"(word));
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return result;
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}
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/* Find First Zero */
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static inline unsigned long ffz(unsigned long word)
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{
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return __ffs(~word);
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}
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/* Find Last bit Set */
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static inline int fls(unsigned long word)
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{
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unsigned long result;
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asm("clz %0,%1" : "=r"(result) : "r"(word));
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return 32 - result;
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}
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unsigned long find_first_zero_bit(const unsigned long *addr,
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unsigned long size);
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unsigned long find_next_zero_bit(const unsigned long *addr,
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unsigned long size,
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unsigned long offset);
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unsigned long find_first_bit(const unsigned long *addr,
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unsigned long size);
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unsigned long find_next_bit(const unsigned long *addr,
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unsigned long size,
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unsigned long offset);
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/*
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* ffs: find first bit set. This is defined the same way as
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* the libc and compiler builtin ffs routines, therefore
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* differs in spirit from the above ffz (man ffs).
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*
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* The difference is that bit numbering starts at 1, and if no bit is set,
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* the function returns 0.
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*/
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static inline int ffs(unsigned long word)
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{
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if(word == 0)
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return 0;
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return __ffs(word) + 1;
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}
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#include <asm-generic/bitops/fls64.h>
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#include <asm-generic/bitops/sched.h>
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#include <asm-generic/bitops/hweight.h>
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#include <asm-generic/bitops/ext2-non-atomic.h>
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#include <asm-generic/bitops/ext2-atomic.h>
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#include <asm-generic/bitops/minix-le.h>
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#endif /* __ASM_AVR32_BITOPS_H */
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