5f0fbf9eca
This is the minimum fixmap interface expected to be implemented by architectures supporting highmem. We have a second level page table already allocated and covering 0xfff00000-0xffffffff because the exception vector page is located at 0xffff0000, and various cache tricks already use some entries above 0xffff0000. Therefore the PTEs covering 0xfff00000-0xfffeffff are free to be used. However the XScale cache flushing code already uses virtual addresses between 0xfffe0000 and 0xfffeffff. So this reserves the 0xfff00000-0xfffdffff range for fixmap stuff. The Documentation/arm/memory.txt information is updated accordingly, including the information about the actual top of DMA memory mapping region which didn't match the code. Signed-off-by: Nicolas Pitre <nico@marvell.com>
35 lines
696 B
C
35 lines
696 B
C
#ifdef CONFIG_MMU
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/* the upper-most page table pointer */
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extern pmd_t *top_pmd;
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#define TOP_PTE(x) pte_offset_kernel(top_pmd, x)
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static inline pmd_t *pmd_off(pgd_t *pgd, unsigned long virt)
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{
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return pmd_offset(pgd, virt);
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}
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static inline pmd_t *pmd_off_k(unsigned long virt)
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{
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return pmd_off(pgd_offset_k(virt), virt);
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}
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struct mem_type {
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unsigned int prot_pte;
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unsigned int prot_l1;
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unsigned int prot_sect;
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unsigned int domain;
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};
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const struct mem_type *get_mem_type(unsigned int type);
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#endif
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struct map_desc;
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struct meminfo;
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struct pglist_data;
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void __init create_mapping(struct map_desc *md);
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void __init bootmem_init(void);
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void reserve_node_zero(struct pglist_data *pgdat);
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