kernel-fxtec-pro1x/arch/powerpc/boot/dts/mpc832x_rdb.dts
Paul Gortmaker 390167efa3 [POWERPC] QE: Explicitly set address-cells and size cells for muram
Currently there are several dts that don't specify address or size
cells for the muram.  This causes dtc to use default values, one of
which is an address-cells of two, and this breaks the parsing of the
muram ranges, which is assuming an address-cells of one. For example:

Warning (reg_format): "reg" property in
/qe@e0100000/muram@10000/data-only@0 has invalid length
(8 bytes) (#address-cells == 2, #size-cells == 1)

Explicitly setting the address and size cells gets it parsed properly
and gets rid of the four dtc warnings.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-28 09:02:09 -06:00

303 lines
6.7 KiB
Text

/*
* MPC832x RDB Device Tree Source
*
* Copyright 2007 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/ {
model = "MPC8323ERDB";
compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8323@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <20>; // 32 bytes
i-cache-line-size = <20>; // 32 bytes
d-cache-size = <4000>; // L1, 16K
i-cache-size = <4000>; // L1, 16K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
};
};
memory {
device_type = "memory";
reg = <00000000 04000000>;
};
soc8323@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
ranges = <0 e0000000 00100000>;
reg = <e0000000 00000200>;
bus-frequency = <0>;
wdt@200 {
device_type = "watchdog";
compatible = "mpc83xx_wdt";
reg = <200 100>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <3000 100>;
interrupts = <e 8>;
interrupt-parent = <&pic>;
dfsrr;
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "ns16550";
reg = <4500 100>;
clock-frequency = <0>;
interrupts = <9 8>;
interrupt-parent = <&pic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "ns16550";
reg = <4600 100>;
clock-frequency = <0>;
interrupts = <a 8>;
interrupt-parent = <&pic>;
};
crypto@30000 {
device_type = "crypto";
model = "SEC2";
compatible = "talitos";
reg = <30000 7000>;
interrupts = <b 8>;
interrupt-parent = <&pic>;
/* Rev. 2.2 */
num-channels = <1>;
channel-fifo-len = <18>;
exec-units-mask = <0000004c>;
descriptor-types-mask = <0122003f>;
};
pic:pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <700 100>;
device_type = "ipic";
};
par_io@1400 {
reg = <1400 100>;
device_type = "par_io";
num-ports = <7>;
ucc2pio:ucc_pin@02 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 4 3 0 2 0 /* MDIO */
3 5 1 0 2 0 /* MDC */
3 15 2 0 1 0 /* RX_CLK (CLK16) */
3 17 2 0 1 0 /* TX_CLK (CLK3) */
0 12 1 0 1 0 /* TxD0 */
0 13 1 0 1 0 /* TxD1 */
0 14 1 0 1 0 /* TxD2 */
0 15 1 0 1 0 /* TxD3 */
0 16 2 0 1 0 /* RxD0 */
0 17 2 0 1 0 /* RxD1 */
0 18 2 0 1 0 /* RxD2 */
0 19 2 0 1 0 /* RxD3 */
0 1a 2 0 1 0 /* RX_ER */
0 1b 1 0 1 0 /* TX_ER */
0 1c 2 0 1 0 /* RX_DV */
0 1d 2 0 1 0 /* COL */
0 1e 1 0 1 0 /* TX_EN */
0 1f 2 0 1 0>; /* CRS */
};
ucc3pio:ucc_pin@03 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 d 2 0 1 0 /* RX_CLK (CLK9) */
3 18 2 0 1 0 /* TX_CLK (CLK10) */
1 0 1 0 1 0 /* TxD0 */
1 1 1 0 1 0 /* TxD1 */
1 2 1 0 1 0 /* TxD2 */
1 3 1 0 1 0 /* TxD3 */
1 4 2 0 1 0 /* RxD0 */
1 5 2 0 1 0 /* RxD1 */
1 6 2 0 1 0 /* RxD2 */
1 7 2 0 1 0 /* RxD3 */
1 8 2 0 1 0 /* RX_ER */
1 9 1 0 1 0 /* TX_ER */
1 a 2 0 1 0 /* RX_DV */
1 b 2 0 1 0 /* COL */
1 c 1 0 1 0 /* TX_EN */
1 d 2 0 1 0>; /* CRS */
};
};
};
qe@e0100000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "qe";
compatible = "fsl,qe";
ranges = <0 e0100000 00100000>;
reg = <e0100000 480>;
brg-frequency = <0>;
bus-frequency = <BCD3D80>;
muram@10000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0 00010000 00004000>;
data-only@0 {
compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data";
reg = <0 4000>;
};
};
spi@4c0 {
cell-index = <0>;
compatible = "fsl,spi";
reg = <4c0 40>;
interrupts = <2>;
interrupt-parent = <&qeic>;
mode = "cpu-qe";
};
spi@500 {
cell-index = <1>;
compatible = "fsl,spi";
reg = <500 40>;
interrupts = <1>;
interrupt-parent = <&qeic>;
mode = "cpu";
};
enet0: ucc@3000 {
device_type = "network";
compatible = "ucc_geth";
model = "UCC";
cell-index = <2>;
device-id = <2>;
reg = <3000 200>;
interrupts = <21>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "clk16";
tx-clock-name = "clk3";
phy-handle = <&phy00>;
pio-handle = <&ucc2pio>;
};
enet1: ucc@2200 {
device_type = "network";
compatible = "ucc_geth";
model = "UCC";
cell-index = <3>;
device-id = <3>;
reg = <2200 200>;
interrupts = <22>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "clk9";
tx-clock-name = "clk10";
phy-handle = <&phy04>;
pio-handle = <&ucc3pio>;
};
mdio@3120 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3120 18>;
compatible = "fsl,ucc-mdio";
phy00:ethernet-phy@00 {
interrupt-parent = <&pic>;
interrupts = <0>;
reg = <0>;
device_type = "ethernet-phy";
};
phy04:ethernet-phy@04 {
interrupt-parent = <&pic>;
interrupts = <0>;
reg = <4>;
device_type = "ethernet-phy";
};
};
qeic:interrupt-controller@80 {
interrupt-controller;
compatible = "fsl,qe-ic";
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <80 80>;
big-endian;
interrupts = <20 8 21 8>; //high:32 low:33
interrupt-parent = <&pic>;
};
};
pci0: pci@e0008500 {
cell-index = <1>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x10 AD16 (USB) */
8000 0 0 1 &pic 11 8
/* IDSEL 0x11 AD17 (Mini1)*/
8800 0 0 1 &pic 12 8
8800 0 0 2 &pic 13 8
8800 0 0 3 &pic 14 8
8800 0 0 4 &pic 30 8
/* IDSEL 0x12 AD18 (PCI/Mini2) */
9000 0 0 1 &pic 13 8
9000 0 0 2 &pic 14 8
9000 0 0 3 &pic 30 8
9000 0 0 4 &pic 11 8>;
interrupt-parent = <&pic>;
interrupts = <42 8>;
bus-range = <0 0>;
ranges = <42000000 0 80000000 80000000 0 10000000
02000000 0 90000000 90000000 0 10000000
01000000 0 d0000000 d0000000 0 04000000>;
clock-frequency = <0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <e0008500 100>;
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
};