53dc80287d
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
95 lines
3 KiB
C
95 lines
3 KiB
C
/*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*
|
|
* Copyright (C) 1994 Waldorf GMBH
|
|
* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
|
|
* Copyright (C) 1996 Paul M. Antoine
|
|
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
|
|
* Copyright (C) 2004 Maciej W. Rozycki
|
|
*/
|
|
#ifndef __ASM_CPU_INFO_H
|
|
#define __ASM_CPU_INFO_H
|
|
|
|
#include <asm/cache.h>
|
|
|
|
#ifdef CONFIG_SGI_IP27
|
|
#include <asm/sn/types.h>
|
|
#endif
|
|
|
|
/*
|
|
* Descriptor for a cache
|
|
*/
|
|
struct cache_desc {
|
|
unsigned int waysize; /* Bytes per way */
|
|
unsigned short sets; /* Number of lines per set */
|
|
unsigned char ways; /* Number of ways */
|
|
unsigned char linesz; /* Size of line in bytes */
|
|
unsigned char waybit; /* Bits to select in a cache set */
|
|
unsigned char flags; /* Flags describing cache properties */
|
|
};
|
|
|
|
/*
|
|
* Flag definitions
|
|
*/
|
|
#define MIPS_CACHE_NOT_PRESENT 0x00000001
|
|
#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
|
|
#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
|
|
#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
|
|
#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
|
|
#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
|
|
|
|
struct cpuinfo_mips {
|
|
unsigned long udelay_val;
|
|
unsigned long asid_cache;
|
|
#if defined(CONFIG_SGI_IP27)
|
|
// cpuid_t p_cpuid; /* PROM assigned cpuid */
|
|
cnodeid_t p_nodeid; /* my node ID in compact-id-space */
|
|
nasid_t p_nasid; /* my node ID in numa-as-id-space */
|
|
unsigned char p_slice; /* Physical position on node board */
|
|
#endif
|
|
#if 0
|
|
unsigned long loops_per_sec;
|
|
unsigned long ipi_count;
|
|
unsigned long irq_attempt[NR_IRQS];
|
|
unsigned long smp_local_irq_count;
|
|
unsigned long prof_multiplier;
|
|
unsigned long prof_counter;
|
|
#endif
|
|
|
|
/*
|
|
* Capability and feature descriptor structure for MIPS CPU
|
|
*/
|
|
unsigned long options;
|
|
unsigned long ases;
|
|
unsigned int processor_id;
|
|
unsigned int fpu_id;
|
|
unsigned int cputype;
|
|
int isa_level;
|
|
int tlbsize;
|
|
struct cache_desc icache; /* Primary I-cache */
|
|
struct cache_desc dcache; /* Primary D or combined I/D cache */
|
|
struct cache_desc scache; /* Secondary cache */
|
|
struct cache_desc tcache; /* Tertiary/split secondary cache */
|
|
#if defined(CONFIG_MIPS_MT_SMTC)
|
|
/*
|
|
* In the MIPS MT "SMTC" model, each TC is considered
|
|
* to be a "CPU" for the purposes of scheduling, but
|
|
* exception resources, ASID spaces, etc, are common
|
|
* to all TCs within the same VPE.
|
|
*/
|
|
int vpe_id; /* Virtual Processor number */
|
|
int tc_id; /* Thread Context number */
|
|
#endif /* CONFIG_MIPS_MT */
|
|
void *data; /* Additional data */
|
|
} __attribute__((aligned(SMP_CACHE_BYTES)));
|
|
|
|
extern struct cpuinfo_mips cpu_data[];
|
|
#define current_cpu_data cpu_data[smp_processor_id()]
|
|
#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
|
|
|
|
extern void cpu_probe(void);
|
|
extern void cpu_report(void);
|
|
|
|
#endif /* __ASM_CPU_INFO_H */
|