29e744d088
After reworking the code responsible for selecting the best DMA transfer mode it is now possible to add generic ide_tune_dma() helper. Convert some IDE PCI host drivers to use it (the ones left need more work). Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
407 lines
11 KiB
C
407 lines
11 KiB
C
/*
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* linux/drivers/ide/pci/aec62xx.c Version 0.21 Apr 21, 2007
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*
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* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
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*
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/hdreg.h>
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#include <linux/ide.h>
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#include <linux/init.h>
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#include <asm/io.h>
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struct chipset_bus_clock_list_entry {
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u8 xfer_speed;
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u8 chipset_settings;
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u8 ultra_settings;
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};
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static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
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{ XFER_UDMA_6, 0x31, 0x07 },
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{ XFER_UDMA_5, 0x31, 0x06 },
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{ XFER_UDMA_4, 0x31, 0x05 },
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{ XFER_UDMA_3, 0x31, 0x04 },
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{ XFER_UDMA_2, 0x31, 0x03 },
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{ XFER_UDMA_1, 0x31, 0x02 },
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{ XFER_UDMA_0, 0x31, 0x01 },
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{ XFER_MW_DMA_2, 0x31, 0x00 },
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{ XFER_MW_DMA_1, 0x31, 0x00 },
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{ XFER_MW_DMA_0, 0x0a, 0x00 },
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{ XFER_PIO_4, 0x31, 0x00 },
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{ XFER_PIO_3, 0x33, 0x00 },
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{ XFER_PIO_2, 0x08, 0x00 },
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{ XFER_PIO_1, 0x0a, 0x00 },
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{ XFER_PIO_0, 0x00, 0x00 },
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{ 0, 0x00, 0x00 }
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};
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static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
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{ XFER_UDMA_6, 0x41, 0x06 },
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{ XFER_UDMA_5, 0x41, 0x05 },
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{ XFER_UDMA_4, 0x41, 0x04 },
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{ XFER_UDMA_3, 0x41, 0x03 },
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{ XFER_UDMA_2, 0x41, 0x02 },
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{ XFER_UDMA_1, 0x41, 0x01 },
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{ XFER_UDMA_0, 0x41, 0x01 },
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{ XFER_MW_DMA_2, 0x41, 0x00 },
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{ XFER_MW_DMA_1, 0x42, 0x00 },
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{ XFER_MW_DMA_0, 0x7a, 0x00 },
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{ XFER_PIO_4, 0x41, 0x00 },
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{ XFER_PIO_3, 0x43, 0x00 },
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{ XFER_PIO_2, 0x78, 0x00 },
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{ XFER_PIO_1, 0x7a, 0x00 },
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{ XFER_PIO_0, 0x70, 0x00 },
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{ 0, 0x00, 0x00 }
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};
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#define BUSCLOCK(D) \
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((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
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/*
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* TO DO: active tuning and correction of cards without a bios.
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*/
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static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
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{
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for ( ; chipset_table->xfer_speed ; chipset_table++)
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if (chipset_table->xfer_speed == speed) {
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return chipset_table->chipset_settings;
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}
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return chipset_table->chipset_settings;
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}
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static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
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{
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for ( ; chipset_table->xfer_speed ; chipset_table++)
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if (chipset_table->xfer_speed == speed) {
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return chipset_table->ultra_settings;
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}
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return chipset_table->ultra_settings;
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}
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static int aec6210_tune_chipset (ide_drive_t *drive, u8 xferspeed)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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u16 d_conf = 0;
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u8 speed = ide_rate_filter(drive, xferspeed);
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u8 ultra = 0, ultra_conf = 0;
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u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
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unsigned long flags;
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local_irq_save(flags);
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/* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
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pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
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tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
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d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
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pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
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tmp1 = 0x00;
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tmp2 = 0x00;
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pci_read_config_byte(dev, 0x54, &ultra);
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tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
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ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
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tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
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pci_write_config_byte(dev, 0x54, tmp2);
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local_irq_restore(flags);
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return(ide_config_drive_speed(drive, speed));
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}
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static int aec6260_tune_chipset (ide_drive_t *drive, u8 xferspeed)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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u8 speed = ide_rate_filter(drive, xferspeed);
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u8 unit = (drive->select.b.unit & 0x01);
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u8 tmp1 = 0, tmp2 = 0;
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u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
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unsigned long flags;
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local_irq_save(flags);
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/* high 4-bits: Active, low 4-bits: Recovery */
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pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
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drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
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pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
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pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
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tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
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ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
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tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
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pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
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local_irq_restore(flags);
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return(ide_config_drive_speed(drive, speed));
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}
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static int aec62xx_tune_chipset (ide_drive_t *drive, u8 speed)
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{
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switch (HWIF(drive)->pci_dev->device) {
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case PCI_DEVICE_ID_ARTOP_ATP865:
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case PCI_DEVICE_ID_ARTOP_ATP865R:
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case PCI_DEVICE_ID_ARTOP_ATP860:
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case PCI_DEVICE_ID_ARTOP_ATP860R:
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return ((int) aec6260_tune_chipset(drive, speed));
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case PCI_DEVICE_ID_ARTOP_ATP850UF:
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return ((int) aec6210_tune_chipset(drive, speed));
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default:
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return -1;
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}
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}
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static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio)
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{
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pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
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(void) aec62xx_tune_chipset(drive, pio + XFER_PIO_0);
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}
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static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
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{
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if (ide_tune_dma(drive))
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return 0;
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if (ide_use_fast_pio(drive))
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aec62xx_tune_drive(drive, 255);
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return -1;
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}
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static int aec62xx_irq_timeout (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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switch(dev->device) {
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case PCI_DEVICE_ID_ARTOP_ATP860:
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case PCI_DEVICE_ID_ARTOP_ATP860R:
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case PCI_DEVICE_ID_ARTOP_ATP865:
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case PCI_DEVICE_ID_ARTOP_ATP865R:
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printk(" AEC62XX time out ");
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default:
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break;
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}
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return 0;
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}
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static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
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{
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int bus_speed = system_bus_clock();
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if (dev->resource[PCI_ROM_RESOURCE].start) {
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pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
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printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
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(unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
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}
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if (bus_speed <= 33)
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pci_set_drvdata(dev, (void *) aec6xxx_33_base);
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else
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pci_set_drvdata(dev, (void *) aec6xxx_34_base);
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/* These are necessary to get AEC6280 Macintosh cards to work */
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if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
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(dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
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u8 reg49h = 0, reg4ah = 0;
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/* Clear reset and test bits. */
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pci_read_config_byte(dev, 0x49, ®49h);
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pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
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/* Enable chip interrupt output. */
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pci_read_config_byte(dev, 0x4a, ®4ah);
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pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
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/* Enable burst mode. */
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pci_read_config_byte(dev, 0x4a, ®4ah);
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pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
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}
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return dev->irq;
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}
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static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
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{
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struct pci_dev *dev = hwif->pci_dev;
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hwif->autodma = 0;
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hwif->tuneproc = &aec62xx_tune_drive;
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hwif->speedproc = &aec62xx_tune_chipset;
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if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF)
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hwif->serialized = hwif->channel;
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if (hwif->mate)
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hwif->mate->serialized = hwif->serialized;
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if (!hwif->dma_base) {
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hwif->drives[0].autotune = 1;
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hwif->drives[1].autotune = 1;
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return;
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}
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hwif->ultra_mask = hwif->cds->udma_mask;
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/* atp865 and atp865r */
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if (hwif->ultra_mask == 0x3f) {
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/* check bit 0x10 of DMA status register */
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if (inb(pci_resource_start(dev, 4) + 2) & 0x10)
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hwif->ultra_mask = 0x7f; /* udma0-6 */
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}
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hwif->mwdma_mask = 0x07;
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hwif->ide_dma_check = &aec62xx_config_drive_xfer_rate;
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hwif->ide_dma_lostirq = &aec62xx_irq_timeout;
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if (!noautodma)
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hwif->autodma = 1;
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hwif->drives[0].autodma = hwif->autodma;
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hwif->drives[1].autodma = hwif->autodma;
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}
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static void __devinit init_dma_aec62xx(ide_hwif_t *hwif, unsigned long dmabase)
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{
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struct pci_dev *dev = hwif->pci_dev;
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if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
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u8 reg54h = 0;
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unsigned long flags;
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spin_lock_irqsave(&ide_lock, flags);
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pci_read_config_byte(dev, 0x54, ®54h);
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pci_write_config_byte(dev, 0x54, reg54h & ~(hwif->channel ? 0xF0 : 0x0F));
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spin_unlock_irqrestore(&ide_lock, flags);
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} else {
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u8 ata66 = 0;
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pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
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if (!(hwif->udma_four))
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hwif->udma_four = (ata66&(hwif->channel?0x02:0x01))?0:1;
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}
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ide_setup_dma(hwif, dmabase, 8);
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}
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static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d)
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{
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return ide_setup_pci_device(dev, d);
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}
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static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d)
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{
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unsigned long bar4reg = pci_resource_start(dev, 4);
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if (inb(bar4reg+2) & 0x10) {
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strcpy(d->name, "AEC6880");
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if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
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strcpy(d->name, "AEC6880R");
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} else {
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strcpy(d->name, "AEC6280");
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if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
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strcpy(d->name, "AEC6280R");
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}
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return ide_setup_pci_device(dev, d);
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}
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static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
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{ /* 0 */
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.name = "AEC6210",
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.init_setup = init_setup_aec62xx,
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.init_chipset = init_chipset_aec62xx,
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.init_hwif = init_hwif_aec62xx,
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.init_dma = init_dma_aec62xx,
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.channels = 2,
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.autodma = AUTODMA,
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.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
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.bootable = OFF_BOARD,
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.udma_mask = 0x07, /* udma0-2 */
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},{ /* 1 */
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.name = "AEC6260",
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.init_setup = init_setup_aec62xx,
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.init_chipset = init_chipset_aec62xx,
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.init_hwif = init_hwif_aec62xx,
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.init_dma = init_dma_aec62xx,
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.channels = 2,
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.autodma = NOAUTODMA,
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.bootable = OFF_BOARD,
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.udma_mask = 0x1f, /* udma0-4 */
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},{ /* 2 */
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.name = "AEC6260R",
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.init_setup = init_setup_aec62xx,
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.init_chipset = init_chipset_aec62xx,
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.init_hwif = init_hwif_aec62xx,
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.init_dma = init_dma_aec62xx,
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.channels = 2,
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.autodma = AUTODMA,
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.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
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.bootable = NEVER_BOARD,
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.udma_mask = 0x1f, /* udma0-4 */
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},{ /* 3 */
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.name = "AEC6X80",
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.init_setup = init_setup_aec6x80,
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.init_chipset = init_chipset_aec62xx,
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.init_hwif = init_hwif_aec62xx,
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.init_dma = init_dma_aec62xx,
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.channels = 2,
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.autodma = AUTODMA,
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.bootable = OFF_BOARD,
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.udma_mask = 0x3f, /* udma0-5 */
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},{ /* 4 */
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.name = "AEC6X80R",
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.init_setup = init_setup_aec6x80,
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.init_chipset = init_chipset_aec62xx,
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.init_hwif = init_hwif_aec62xx,
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.init_dma = init_dma_aec62xx,
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.channels = 2,
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.autodma = AUTODMA,
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.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
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.bootable = OFF_BOARD,
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.udma_mask = 0x3f, /* udma0-5 */
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}
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};
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/**
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* aec62xx_init_one - called when a AEC is found
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* @dev: the aec62xx device
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* @id: the matching pci id
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*
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* Called when the PCI registration layer (or the IDE initialization)
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* finds a device matching our IDE device tables.
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*/
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static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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ide_pci_device_t *d = &aec62xx_chipsets[id->driver_data];
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return d->init_setup(dev, d);
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}
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static struct pci_device_id aec62xx_pci_tbl[] = {
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{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
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{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
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{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
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{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
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{ PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
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static struct pci_driver driver = {
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.name = "AEC62xx_IDE",
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.id_table = aec62xx_pci_tbl,
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.probe = aec62xx_init_one,
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};
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static int __init aec62xx_ide_init(void)
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{
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return ide_pci_register_driver(&driver);
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}
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module_init(aec62xx_ide_init);
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MODULE_AUTHOR("Andre Hedrick");
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MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
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MODULE_LICENSE("GPL");
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