38ce73ebd7
Add CP6 enable/disable sequences to the timekeeping code and the IRQ code. As a result, we can't depend on CP6 access being enabled when we enter get_irqnr_and_base anymore, so switch the latter over to using memory-mapped accesses for now. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
98 lines
2.4 KiB
C
98 lines
2.4 KiB
C
/*
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* arch/arm/plat-iop/time.c
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*
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* Timer code for IOP32x and IOP33x based systems
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*
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* Author: Deepak Saxena <dsaxena@mvista.com>
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*
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* Copyright 2002-2003 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <linux/init.h>
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#include <linux/timex.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#ifdef CONFIG_ARCH_IOP32X
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#define IRQ_IOP3XX_TIMER0 IRQ_IOP321_TIMER0
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#else
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#ifdef CONFIG_ARCH_IOP33X
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#define IRQ_IOP3XX_TIMER0 IRQ_IOP331_TIMER0
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#endif
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#endif
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static unsigned long ticks_per_jiffy;
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static unsigned long ticks_per_usec;
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static unsigned long next_jiffy_time;
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unsigned long iop3xx_gettimeoffset(void)
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{
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unsigned long offset;
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offset = next_jiffy_time - *IOP3XX_TU_TCR1;
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return offset / ticks_per_usec;
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}
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static irqreturn_t
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iop3xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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write_seqlock(&xtime_lock);
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1));
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iop3xx_cp6_disable();
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while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1)
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>= ticks_per_jiffy) {
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timer_tick(regs);
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next_jiffy_time -= ticks_per_jiffy;
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}
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write_sequnlock(&xtime_lock);
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return IRQ_HANDLED;
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}
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static struct irqaction iop3xx_timer_irq = {
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.name = "IOP3XX Timer Tick",
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.handler = iop3xx_timer_interrupt,
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.flags = IRQF_DISABLED | IRQF_TIMER,
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};
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void __init iop3xx_init_time(unsigned long tick_rate)
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{
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u32 timer_ctl;
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ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
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ticks_per_usec = tick_rate / 1000000;
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next_jiffy_time = 0xffffffff;
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timer_ctl = IOP3XX_TMR_EN | IOP3XX_TMR_PRIVILEGED |
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IOP3XX_TMR_RELOAD | IOP3XX_TMR_RATIO_1_1;
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/*
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* We use timer 0 for our timer interrupt, and timer 1 as
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* monotonic counter for tracking missed jiffies.
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*/
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1));
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asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl));
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asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff));
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asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl));
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iop3xx_cp6_disable();
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setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq);
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}
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