152d018282
Add the platform-specific code for enabling SWIOTLB if needed on P2020DS, MPC85xx DS, and MPC85xx MDS boards as they are capable of having >4G of memory. We determine if we need to enable swiotlb based on how much memory is in the board and if it exceeds 4G or what we can map via PCI inbound windows. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
313 lines
7.1 KiB
C
313 lines
7.1 KiB
C
/*
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* MPC85xx DS Board Setup
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*
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* Author Xianghua Xiao (x.xiao@freescale.com)
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* Roy Zang <tie-fei.zang@freescale.com>
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* - Add PCI/PCI Exprees support
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* Copyright 2007 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/delay.h>
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#include <linux/seq_file.h>
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#include <linux/interrupt.h>
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#include <linux/of_platform.h>
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#include <linux/lmb.h>
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#include <asm/system.h>
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#include <asm/time.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <mm/mmu_decl.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <asm/i8259.h>
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#include <asm/swiotlb.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
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#else
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#define DBG(fmt, args...)
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#endif
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#ifdef CONFIG_PPC_I8259
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static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
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{
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unsigned int cascade_irq = i8259_irq();
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if (cascade_irq != NO_IRQ) {
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generic_handle_irq(cascade_irq);
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}
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desc->chip->eoi(irq);
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}
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#endif /* CONFIG_PPC_I8259 */
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void __init mpc85xx_ds_pic_init(void)
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{
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struct mpic *mpic;
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struct resource r;
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struct device_node *np;
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#ifdef CONFIG_PPC_I8259
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struct device_node *cascade_node = NULL;
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int cascade_irq;
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#endif
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unsigned long root = of_get_flat_dt_root();
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np = of_find_node_by_type(NULL, "open-pic");
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if (np == NULL) {
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printk(KERN_ERR "Could not find open-pic node\n");
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return;
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}
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if (of_address_to_resource(np, 0, &r)) {
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printk(KERN_ERR "Failed to map mpic register space\n");
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of_node_put(np);
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return;
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}
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if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
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mpic = mpic_alloc(np, r.start,
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MPIC_PRIMARY |
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MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS,
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0, 256, " OpenPIC ");
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} else {
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mpic = mpic_alloc(np, r.start,
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MPIC_PRIMARY | MPIC_WANTS_RESET |
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MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
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MPIC_SINGLE_DEST_CPU,
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0, 256, " OpenPIC ");
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}
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BUG_ON(mpic == NULL);
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of_node_put(np);
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mpic_init(mpic);
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#ifdef CONFIG_PPC_I8259
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/* Initialize the i8259 controller */
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for_each_node_by_type(np, "interrupt-controller")
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if (of_device_is_compatible(np, "chrp,iic")) {
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cascade_node = np;
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break;
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}
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if (cascade_node == NULL) {
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printk(KERN_DEBUG "Could not find i8259 PIC\n");
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return;
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}
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cascade_irq = irq_of_parse_and_map(cascade_node, 0);
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if (cascade_irq == NO_IRQ) {
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printk(KERN_ERR "Failed to map cascade interrupt\n");
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return;
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}
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DBG("mpc85xxds: cascade mapped to irq %d\n", cascade_irq);
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i8259_init(cascade_node, 0);
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of_node_put(cascade_node);
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set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade);
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#endif /* CONFIG_PPC_I8259 */
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}
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#ifdef CONFIG_PCI
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static int primary_phb_addr;
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extern int uli_exclude_device(struct pci_controller *hose,
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u_char bus, u_char devfn);
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static int mpc85xx_exclude_device(struct pci_controller *hose,
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u_char bus, u_char devfn)
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{
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struct device_node* node;
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struct resource rsrc;
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node = hose->dn;
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of_address_to_resource(node, 0, &rsrc);
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if ((rsrc.start & 0xfffff) == primary_phb_addr) {
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return uli_exclude_device(hose, bus, devfn);
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}
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return PCIBIOS_SUCCESSFUL;
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}
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#endif /* CONFIG_PCI */
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/*
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* Setup the architecture
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*/
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#ifdef CONFIG_SMP
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extern void __init mpc85xx_smp_init(void);
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#endif
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static void __init mpc85xx_ds_setup_arch(void)
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{
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#ifdef CONFIG_PCI
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struct device_node *np;
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struct pci_controller *hose;
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#endif
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dma_addr_t max = 0xffffffff;
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if (ppc_md.progress)
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ppc_md.progress("mpc85xx_ds_setup_arch()", 0);
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#ifdef CONFIG_PCI
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for_each_node_by_type(np, "pci") {
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if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
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of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
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of_device_is_compatible(np, "fsl,p2020-pcie")) {
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struct resource rsrc;
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of_address_to_resource(np, 0, &rsrc);
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if ((rsrc.start & 0xfffff) == primary_phb_addr)
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fsl_add_bridge(np, 1);
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else
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fsl_add_bridge(np, 0);
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hose = pci_find_hose_for_OF_device(np);
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max = min(max, hose->dma_window_base_cur +
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hose->dma_window_size);
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}
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}
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ppc_md.pci_exclude_device = mpc85xx_exclude_device;
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#endif
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#ifdef CONFIG_SMP
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mpc85xx_smp_init();
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#endif
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#ifdef CONFIG_SWIOTLB
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if (lmb_end_of_DRAM() > max) {
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ppc_swiotlb_enable = 1;
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set_pci_dma_ops(&swiotlb_pci_dma_ops);
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}
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#endif
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printk("MPC85xx DS board from Freescale Semiconductor\n");
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}
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init mpc8544_ds_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (of_flat_dt_is_compatible(root, "MPC8544DS")) {
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#ifdef CONFIG_PCI
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primary_phb_addr = 0xb000;
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#endif
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return 1;
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}
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return 0;
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}
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static struct of_device_id __initdata mpc85xxds_ids[] = {
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{ .type = "soc", },
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{ .compatible = "soc", },
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{ .compatible = "simple-bus", },
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{ .compatible = "gianfar", },
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{},
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};
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static int __init mpc85xxds_publish_devices(void)
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{
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return of_platform_bus_probe(NULL, mpc85xxds_ids, NULL);
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}
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machine_device_initcall(mpc8544_ds, mpc85xxds_publish_devices);
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machine_device_initcall(mpc8572_ds, mpc85xxds_publish_devices);
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machine_device_initcall(p2020_ds, mpc85xxds_publish_devices);
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machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier);
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machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier);
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machine_arch_initcall(p2020_ds, swiotlb_setup_bus_notifier);
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init mpc8572_ds_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS")) {
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#ifdef CONFIG_PCI
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primary_phb_addr = 0x8000;
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#endif
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return 1;
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}
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return 0;
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}
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init p2020_ds_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (of_flat_dt_is_compatible(root, "fsl,P2020DS")) {
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#ifdef CONFIG_PCI
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primary_phb_addr = 0x9000;
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#endif
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return 1;
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}
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return 0;
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}
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define_machine(mpc8544_ds) {
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.name = "MPC8544 DS",
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.probe = mpc8544_ds_probe,
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.setup_arch = mpc85xx_ds_setup_arch,
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.init_IRQ = mpc85xx_ds_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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define_machine(mpc8572_ds) {
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.name = "MPC8572 DS",
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.probe = mpc8572_ds_probe,
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.setup_arch = mpc85xx_ds_setup_arch,
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.init_IRQ = mpc85xx_ds_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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define_machine(p2020_ds) {
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.name = "P2020 DS",
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.probe = p2020_ds_probe,
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.setup_arch = mpc85xx_ds_setup_arch,
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.init_IRQ = mpc85xx_ds_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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