175854be81
Hello,
Introduced by:
commit fff147208b
Author: Eric Miao <eric.miao@marvell.com>
Date: Fri Sep 5 22:15:23 2008 +0800
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Eric Miao <eric.miao@marvell.com>
191 lines
8.3 KiB
C
191 lines
8.3 KiB
C
/*
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* Hardware specific definitions for SL-Cx000 series of PDAs
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*
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* Copyright (c) 2005 Alexander Wykes
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* Copyright (c) 2005 Richard Purdie
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*
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* Based on Sharp's 2.4 kernel patches
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __ASM_ARCH_SPITZ_H
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#define __ASM_ARCH_SPITZ_H 1
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#endif
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#include <linux/fb.h>
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#include <linux/gpio.h>
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/* Spitz/Akita GPIOs */
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#define SPITZ_GPIO_KEY_INT (0) /* Key Interrupt */
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#define SPITZ_GPIO_RESET (1)
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#define SPITZ_GPIO_nSD_DETECT (9)
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#define SPITZ_GPIO_TP_INT (11) /* Touch Panel interrupt */
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#define SPITZ_GPIO_AK_INT (13) /* Remote Control */
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#define SPITZ_GPIO_ADS7846_CS (14)
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#define SPITZ_GPIO_SYNC (16)
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#define SPITZ_GPIO_MAX1111_CS (20)
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#define SPITZ_GPIO_FATAL_BAT (21)
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#define SPITZ_GPIO_HSYNC (22)
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#define SPITZ_GPIO_nSD_CLK (32)
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#define SPITZ_GPIO_USB_DEVICE (35)
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#define SPITZ_GPIO_USB_HOST (37)
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#define SPITZ_GPIO_USB_CONNECT (41)
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#define SPITZ_GPIO_LCDCON_CS (53)
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#define SPITZ_GPIO_nPCE (54)
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#define SPITZ_GPIO_nSD_WP (81)
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#define SPITZ_GPIO_ON_RESET (89)
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#define SPITZ_GPIO_BAT_COVER (90)
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#define SPITZ_GPIO_CF_CD (94)
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#define SPITZ_GPIO_ON_KEY (95)
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#define SPITZ_GPIO_SWA (97)
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#define SPITZ_GPIO_SWB (96)
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#define SPITZ_GPIO_CHRG_FULL (101)
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#define SPITZ_GPIO_CO (101)
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#define SPITZ_GPIO_CF_IRQ (105)
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#define SPITZ_GPIO_AC_IN (115)
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#define SPITZ_GPIO_HP_IN (116)
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/* Spitz Only GPIOs */
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#define SPITZ_GPIO_CF2_IRQ (106) /* CF slot1 Ready */
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#define SPITZ_GPIO_CF2_CD (93)
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/* Spitz/Akita Keyboard Definitions */
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#define SPITZ_KEY_STROBE_NUM (11)
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#define SPITZ_KEY_SENSE_NUM (7)
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#define SPITZ_GPIO_G0_STROBE_BIT 0x0f800000
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#define SPITZ_GPIO_G1_STROBE_BIT 0x00100000
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#define SPITZ_GPIO_G2_STROBE_BIT 0x01000000
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#define SPITZ_GPIO_G3_STROBE_BIT 0x00041880
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#define SPITZ_GPIO_G0_SENSE_BIT 0x00021000
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#define SPITZ_GPIO_G1_SENSE_BIT 0x000000d4
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#define SPITZ_GPIO_G2_SENSE_BIT 0x08000000
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#define SPITZ_GPIO_G3_SENSE_BIT 0x00000000
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#define SPITZ_GPIO_KEY_STROBE0 88
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#define SPITZ_GPIO_KEY_STROBE1 23
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#define SPITZ_GPIO_KEY_STROBE2 24
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#define SPITZ_GPIO_KEY_STROBE3 25
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#define SPITZ_GPIO_KEY_STROBE4 26
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#define SPITZ_GPIO_KEY_STROBE5 27
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#define SPITZ_GPIO_KEY_STROBE6 52
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#define SPITZ_GPIO_KEY_STROBE7 103
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#define SPITZ_GPIO_KEY_STROBE8 107
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#define SPITZ_GPIO_KEY_STROBE9 108
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#define SPITZ_GPIO_KEY_STROBE10 114
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#define SPITZ_GPIO_KEY_SENSE0 12
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#define SPITZ_GPIO_KEY_SENSE1 17
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#define SPITZ_GPIO_KEY_SENSE2 91
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#define SPITZ_GPIO_KEY_SENSE3 34
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#define SPITZ_GPIO_KEY_SENSE4 36
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#define SPITZ_GPIO_KEY_SENSE5 38
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#define SPITZ_GPIO_KEY_SENSE6 39
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/* Spitz Scoop Device (No. 1) GPIOs */
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/* Suspend States in comments */
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#define SPITZ_SCP_LED_GREEN SCOOP_GPCR_PA11 /* Keep */
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#define SPITZ_SCP_JK_B SCOOP_GPCR_PA12 /* Keep */
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#define SPITZ_SCP_CHRG_ON SCOOP_GPCR_PA13 /* Keep */
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#define SPITZ_SCP_MUTE_L SCOOP_GPCR_PA14 /* Low */
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#define SPITZ_SCP_MUTE_R SCOOP_GPCR_PA15 /* Low */
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#define SPITZ_SCP_CF_POWER SCOOP_GPCR_PA16 /* Keep */
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#define SPITZ_SCP_LED_ORANGE SCOOP_GPCR_PA17 /* Keep */
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#define SPITZ_SCP_JK_A SCOOP_GPCR_PA18 /* Low */
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#define SPITZ_SCP_ADC_TEMP_ON SCOOP_GPCR_PA19 /* Low */
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#define SPITZ_SCP_IO_DIR (SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \
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SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | \
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SPITZ_SCP_CF_POWER | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
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#define SPITZ_SCP_IO_OUT (SPITZ_SCP_CHRG_ON | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R)
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#define SPITZ_SCP_SUS_CLR (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
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#define SPITZ_SCP_SUS_SET 0
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#define SPITZ_SCP_GPIO_BASE (NR_BUILTIN_GPIO)
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#define SPITZ_GPIO_LED_GREEN (SPITZ_SCP_GPIO_BASE + 0)
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#define SPITZ_GPIO_JK_B (SPITZ_SCP_GPIO_BASE + 1)
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#define SPITZ_GPIO_CHRG_ON (SPITZ_SCP_GPIO_BASE + 2)
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#define SPITZ_GPIO_MUTE_L (SPITZ_SCP_GPIO_BASE + 3)
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#define SPITZ_GPIO_MUTE_R (SPITZ_SCP_GPIO_BASE + 4)
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#define SPITZ_GPIO_CF_POWER (SPITZ_SCP_GPIO_BASE + 5)
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#define SPITZ_GPIO_LED_ORANGE (SPITZ_SCP_GPIO_BASE + 6)
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#define SPITZ_GPIO_JK_A (SPITZ_SCP_GPIO_BASE + 7)
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#define SPITZ_GPIO_ADC_TEMP_ON (SPITZ_SCP_GPIO_BASE + 8)
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/* Spitz Scoop Device (No. 2) GPIOs */
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/* Suspend States in comments */
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#define SPITZ_SCP2_IR_ON SCOOP_GPCR_PA11 /* High */
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#define SPITZ_SCP2_AKIN_PULLUP SCOOP_GPCR_PA12 /* Keep */
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#define SPITZ_SCP2_RESERVED_1 SCOOP_GPCR_PA13 /* High */
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#define SPITZ_SCP2_RESERVED_2 SCOOP_GPCR_PA14 /* Low */
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#define SPITZ_SCP2_RESERVED_3 SCOOP_GPCR_PA15 /* Low */
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#define SPITZ_SCP2_RESERVED_4 SCOOP_GPCR_PA16 /* Low */
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#define SPITZ_SCP2_BACKLIGHT_CONT SCOOP_GPCR_PA17 /* Low */
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#define SPITZ_SCP2_BACKLIGHT_ON SCOOP_GPCR_PA18 /* Low */
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#define SPITZ_SCP2_MIC_BIAS SCOOP_GPCR_PA19 /* Low */
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#define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \
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SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
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SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
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#define SPITZ_SCP2_IO_OUT (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1)
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#define SPITZ_SCP2_SUS_CLR (SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \
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SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
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#define SPITZ_SCP2_SUS_SET (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1)
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#define SPITZ_SCP2_GPIO_BASE (NR_BUILTIN_GPIO + 12)
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#define SPITZ_GPIO_IR_ON (SPITZ_SCP2_GPIO_BASE + 0)
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#define SPITZ_GPIO_AKIN_PULLUP (SPITZ_SCP2_GPIO_BASE + 1)
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#define SPITZ_GPIO_RESERVED_1 (SPITZ_SCP2_GPIO_BASE + 2)
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#define SPITZ_GPIO_RESERVED_2 (SPITZ_SCP2_GPIO_BASE + 3)
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#define SPITZ_GPIO_RESERVED_3 (SPITZ_SCP2_GPIO_BASE + 4)
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#define SPITZ_GPIO_RESERVED_4 (SPITZ_SCP2_GPIO_BASE + 5)
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#define SPITZ_GPIO_BACKLIGHT_CONT (SPITZ_SCP2_GPIO_BASE + 6)
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#define SPITZ_GPIO_BACKLIGHT_ON (SPITZ_SCP2_GPIO_BASE + 7)
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#define SPITZ_GPIO_MIC_BIAS (SPITZ_SCP2_GPIO_BASE + 8)
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/* Akita IO Expander GPIOs */
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#define AKITA_IOEXP_GPIO_BASE (NR_BUILTIN_GPIO + 12)
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#define AKITA_GPIO_RESERVED_0 (AKITA_IOEXP_GPIO_BASE + 0)
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#define AKITA_GPIO_RESERVED_1 (AKITA_IOEXP_GPIO_BASE + 1)
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#define AKITA_GPIO_MIC_BIAS (AKITA_IOEXP_GPIO_BASE + 2)
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#define AKITA_GPIO_BACKLIGHT_ON (AKITA_IOEXP_GPIO_BASE + 3)
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#define AKITA_GPIO_BACKLIGHT_CONT (AKITA_IOEXP_GPIO_BASE + 4)
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#define AKITA_GPIO_AKIN_PULLUP (AKITA_IOEXP_GPIO_BASE + 5)
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#define AKITA_GPIO_IR_ON (AKITA_IOEXP_GPIO_BASE + 6)
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#define AKITA_GPIO_RESERVED_7 (AKITA_IOEXP_GPIO_BASE + 7)
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/* Spitz IRQ Definitions */
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#define SPITZ_IRQ_GPIO_KEY_INT IRQ_GPIO(SPITZ_GPIO_KEY_INT)
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#define SPITZ_IRQ_GPIO_AC_IN IRQ_GPIO(SPITZ_GPIO_AC_IN)
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#define SPITZ_IRQ_GPIO_AK_INT IRQ_GPIO(SPITZ_GPIO_AK_INT)
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#define SPITZ_IRQ_GPIO_HP_IN IRQ_GPIO(SPITZ_GPIO_HP_IN)
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#define SPITZ_IRQ_GPIO_TP_INT IRQ_GPIO(SPITZ_GPIO_TP_INT)
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#define SPITZ_IRQ_GPIO_SYNC IRQ_GPIO(SPITZ_GPIO_SYNC)
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#define SPITZ_IRQ_GPIO_ON_KEY IRQ_GPIO(SPITZ_GPIO_ON_KEY)
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#define SPITZ_IRQ_GPIO_SWA IRQ_GPIO(SPITZ_GPIO_SWA)
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#define SPITZ_IRQ_GPIO_SWB IRQ_GPIO(SPITZ_GPIO_SWB)
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#define SPITZ_IRQ_GPIO_BAT_COVER IRQ_GPIO(SPITZ_GPIO_BAT_COVER)
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#define SPITZ_IRQ_GPIO_FATAL_BAT IRQ_GPIO(SPITZ_GPIO_FATAL_BAT)
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#define SPITZ_IRQ_GPIO_CO IRQ_GPIO(SPITZ_GPIO_CO)
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#define SPITZ_IRQ_GPIO_CF_IRQ IRQ_GPIO(SPITZ_GPIO_CF_IRQ)
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#define SPITZ_IRQ_GPIO_CF_CD IRQ_GPIO(SPITZ_GPIO_CF_CD)
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#define SPITZ_IRQ_GPIO_CF2_IRQ IRQ_GPIO(SPITZ_GPIO_CF2_IRQ)
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#define SPITZ_IRQ_GPIO_nSD_INT IRQ_GPIO(SPITZ_GPIO_nSD_INT)
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#define SPITZ_IRQ_GPIO_nSD_DETECT IRQ_GPIO(SPITZ_GPIO_nSD_DETECT)
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/*
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* Shared data structures
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*/
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extern struct platform_device spitzscoop_device;
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extern struct platform_device spitzscoop2_device;
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extern struct platform_device spitzssp_device;
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extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
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