150 lines
3.8 KiB
ArmAsm
150 lines
3.8 KiB
ArmAsm
/*
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* DRAM/SDRAM initialization - alter with care
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* This file is intended to be included from other assembler files
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*
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* Note: This file may not modify r9 because r9 is used to carry
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* information from the decompresser to the kernel
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*
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* Copyright (C) 2000, 2001 Axis Communications AB
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*
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* Authors: Mikael Starvik (starvik@axis.com)
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*
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*/
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/* Just to be certain the config file is included, we include it here
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* explicitly instead of depending on it being included in the file that
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* uses this code.
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*/
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;; WARNING! The registers r8 and r9 are used as parameters carrying
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;; information from the decompressor (if the kernel was compressed).
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;; They should not be used in the code below.
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#ifndef CONFIG_SVINTO_SIM
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move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
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move.d $r0, [R_WAITSTATES]
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move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
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move.d $r0, [R_BUS_CONFIG]
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#ifndef CONFIG_ETRAX_SDRAM
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move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
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move.d $r0, [R_DRAM_CONFIG]
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move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
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move.d $r0, [R_DRAM_TIMING]
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#else
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;; Samsung SDRAMs seem to require to be initialized twice to work properly.
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moveq 2, $r6
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_sdram_init:
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; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
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; Bank configuration
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move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0
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move.d $r0, [R_SDRAM_CONFIG]
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; Calculate value of mrs_data
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; CAS latency = 2 && bus_width = 32 => 0x40
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; CAS latency = 3 && bus_width = 32 => 0x60
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; CAS latency = 2 && bus_width = 16 => 0x20
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; CAS latency = 3 && bus_width = 16 => 0x30
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; Check if value is already supplied in kernel config
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move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r2
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and.d 0x00ff0000, $r2
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bne _set_timing
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lsrq 16, $r2
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move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
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move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
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move.d $r1, $r3
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and.d 0x03, $r1 ; Get CAS latency
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and.d 0x1000, $r3 ; 50 or 100 MHz?
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beq _speed_50
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nop
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_speed_100:
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cmp.d 0x00, $r1 ; CAS latency = 2?
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beq _bw_check
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nop
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or.d 0x20, $r2 ; CAS latency = 3
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ba _bw_check
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nop
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_speed_50:
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cmp.d 0x01, $r1 ; CAS latency = 2?
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beq _bw_check
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nop
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or.d 0x20, $r2 ; CAS latency = 3
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_bw_check:
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move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r1
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and.d 0x800000, $r1 ; DRAM width is bit 23
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bne _set_timing
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nop
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lsrq 1, $r2 ; 16 bits. Shift down value.
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; Set timing parameters. Starts master clock
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_set_timing:
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move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
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and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
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or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
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move.d $r1, $r5
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or.d 0x0000c000, $r1 ; ref = disable
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lslq 16, $r2 ; mrs data starts at bit 16
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or.d $r2, $r1
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move.d $r1, [R_SDRAM_TIMING]
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; Wait 200us
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move.d 10000, $r2
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1: bne 1b
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subq 1, $r2
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; Issue initialization command sequence
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move.d _sdram_commands_start, $r2
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and.d 0x000fffff, $r2 ; Make sure commands are read from flash
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move.d _sdram_commands_end, $r3
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and.d 0x000fffff, $r3
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1: clear.d $r4
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move.b [$r2+], $r4
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lslq 9, $r4 ; Command starts at bit 9
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or.d $r1, $r4
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move.d $r4, [R_SDRAM_TIMING]
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nop ; Wait five nop cycles between each command
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nop
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nop
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nop
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nop
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cmp.d $r2, $r3
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bne 1b
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nop
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move.d $r5, [R_SDRAM_TIMING]
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subq 1, $r6
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bne _sdram_init
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nop
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ba _sdram_commands_end
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nop
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_sdram_commands_start:
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.byte 3 ; Precharge
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.byte 0 ; nop
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.byte 2 ; refresh
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.byte 0 ; nop
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.byte 2 ; refresh
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.byte 0 ; nop
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.byte 2 ; refresh
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.byte 0 ; nop
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.byte 2 ; refresh
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.byte 0 ; nop
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.byte 2 ; refresh
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.byte 0 ; nop
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.byte 2 ; refresh
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.byte 0 ; nop
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.byte 2 ; refresh
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.byte 0 ; nop
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.byte 2 ; refresh
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.byte 0 ; nop
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.byte 1 ; mrs
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.byte 0 ; nop
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_sdram_commands_end:
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#endif
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#endif
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