eb0cd5fd29
The architecture allows for "Book-E" style debug interrupts to either go to critial interrupts of their own debug interrupt level. To allow for a dynamic kernel to support machines of either type we want to be able to compile in the interrupt handling code for both exception levels. Towards this goal we renamed the debug handling macros to specify the interrupt level in their name (DEBUG_CRIT_EXCEPTION/DebugCrit and DEBUG_DEBUG_EXCEPTION/DebugDebug). Additionally, on the Freescale Book-e parts we expanded the exception stacks to cover the maximum case of needing three exception stacks (normal, machine check and debug). There is some kernel text space optimization to be gained if a kernel is configured for a specific Freescale implementation but we aren't handling that now to allow for the single kernel image support. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
747 lines
19 KiB
ArmAsm
747 lines
19 KiB
ArmAsm
/*
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* Kernel execution entry point code.
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*
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* Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
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* Initial PowerPC version.
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* Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Rewritten for PReP
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* Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
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* Low-level exception handers, MMU support, and rewrite.
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* Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
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* PowerPC 8xx modifications.
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* Copyright (c) 1998-1999 TiVo, Inc.
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* PowerPC 403GCX modifications.
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* Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
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* PowerPC 403GCX/405GP modifications.
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* Copyright 2000 MontaVista Software Inc.
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* PPC405 modifications
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* PowerPC 403GCX/405GP modifications.
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* Author: MontaVista Software, Inc.
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* frank_rowand@mvista.com or source@mvista.com
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* debbie_chu@mvista.com
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* Copyright 2002-2005 MontaVista Software, Inc.
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* PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/pgtable.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include "head_booke.h"
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/* As with the other PowerPC ports, it is expected that when code
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* execution begins here, the following registers contain valid, yet
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* optional, information:
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*
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* r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
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* r4 - Starting address of the init RAM disk
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* r5 - Ending address of the init RAM disk
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* r6 - Start of kernel command line string (e.g. "mem=128")
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* r7 - End of kernel command line string
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*
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*/
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.section .text.head, "ax"
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_ENTRY(_stext);
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_ENTRY(_start);
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/*
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* Reserve a word at a fixed location to store the address
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* of abatron_pteptrs
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*/
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nop
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/*
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* Save parameters we are passed
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*/
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mr r31,r3
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mr r30,r4
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mr r29,r5
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mr r28,r6
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mr r27,r7
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li r24,0 /* CPU number */
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/*
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* Set up the initial MMU state
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*
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* We are still executing code at the virtual address
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* mappings set by the firmware for the base of RAM.
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*
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* We first invalidate all TLB entries but the one
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* we are running from. We then load the KERNELBASE
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* mappings so we can begin to use kernel addresses
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* natively and so the interrupt vector locations are
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* permanently pinned (necessary since Book E
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* implementations always have translation enabled).
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*
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* TODO: Use the known TLB entry we are running from to
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* determine which physical region we are located
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* in. This can be used to determine where in RAM
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* (on a shared CPU system) or PCI memory space
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* (on a DRAMless system) we are located.
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* For now, we assume a perfect world which means
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* we are located at the base of DRAM (physical 0).
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*/
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/*
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* Search TLB for entry that we are currently using.
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* Invalidate all entries but the one we are using.
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*/
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/* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */
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mfspr r3,SPRN_PID /* Get PID */
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mfmsr r4 /* Get MSR */
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andi. r4,r4,MSR_IS@l /* TS=1? */
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beq wmmucr /* If not, leave STS=0 */
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oris r3,r3,PPC44x_MMUCR_STS@h /* Set STS=1 */
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wmmucr: mtspr SPRN_MMUCR,r3 /* Put MMUCR */
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sync
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bl invstr /* Find our address */
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invstr: mflr r5 /* Make it accessible */
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tlbsx r23,0,r5 /* Find entry we are in */
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li r4,0 /* Start at TLB entry 0 */
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li r3,0 /* Set PAGEID inval value */
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1: cmpw r23,r4 /* Is this our entry? */
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beq skpinv /* If so, skip the inval */
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tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
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skpinv: addi r4,r4,1 /* Increment */
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cmpwi r4,64 /* Are we done? */
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bne 1b /* If not, repeat */
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isync /* If so, context change */
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/*
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* Configure and load pinned entry into TLB slot 63.
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*/
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lis r3,PAGE_OFFSET@h
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ori r3,r3,PAGE_OFFSET@l
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/* Kernel is at the base of RAM */
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li r4, 0 /* Load the kernel physical address */
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/* Load the kernel PID = 0 */
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li r0,0
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mtspr SPRN_PID,r0
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sync
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/* Initialize MMUCR */
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li r5,0
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mtspr SPRN_MMUCR,r5
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sync
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/* pageid fields */
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clrrwi r3,r3,10 /* Mask off the effective page number */
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ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M
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/* xlat fields */
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clrrwi r4,r4,10 /* Mask off the real page number */
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/* ERPN is 0 for first 4GB page */
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/* attrib fields */
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/* Added guarded bit to protect against speculative loads/stores */
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li r5,0
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ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
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li r0,63 /* TLB slot 63 */
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tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */
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tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */
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tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */
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/* Force context change */
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mfmsr r0
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mtspr SPRN_SRR1, r0
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lis r0,3f@h
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ori r0,r0,3f@l
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mtspr SPRN_SRR0,r0
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sync
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rfi
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/* If necessary, invalidate original entry we used */
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3: cmpwi r23,63
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beq 4f
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li r6,0
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tlbwe r6,r23,PPC44x_TLB_PAGEID
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isync
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4:
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#ifdef CONFIG_PPC_EARLY_DEBUG_44x
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/* Add UART mapping for early debug. */
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/* pageid fields */
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lis r3,PPC44x_EARLY_DEBUG_VIRTADDR@h
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ori r3,r3,PPC44x_TLB_VALID|PPC44x_TLB_TS|PPC44x_TLB_64K
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/* xlat fields */
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lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h
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ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH
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/* attrib fields */
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li r5,(PPC44x_TLB_SW|PPC44x_TLB_SR|PPC44x_TLB_I|PPC44x_TLB_G)
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li r0,62 /* TLB slot 0 */
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tlbwe r3,r0,PPC44x_TLB_PAGEID
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tlbwe r4,r0,PPC44x_TLB_XLAT
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tlbwe r5,r0,PPC44x_TLB_ATTRIB
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/* Force context change */
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isync
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#endif /* CONFIG_PPC_EARLY_DEBUG_44x */
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/* Establish the interrupt vector offsets */
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SET_IVOR(0, CriticalInput);
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SET_IVOR(1, MachineCheck);
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SET_IVOR(2, DataStorage);
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SET_IVOR(3, InstructionStorage);
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SET_IVOR(4, ExternalInput);
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SET_IVOR(5, Alignment);
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SET_IVOR(6, Program);
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SET_IVOR(7, FloatingPointUnavailable);
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SET_IVOR(8, SystemCall);
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SET_IVOR(9, AuxillaryProcessorUnavailable);
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SET_IVOR(10, Decrementer);
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SET_IVOR(11, FixedIntervalTimer);
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SET_IVOR(12, WatchdogTimer);
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SET_IVOR(13, DataTLBError);
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SET_IVOR(14, InstructionTLBError);
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SET_IVOR(15, DebugCrit);
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/* Establish the interrupt vector base */
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lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
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mtspr SPRN_IVPR,r4
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/*
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* This is where the main kernel code starts.
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*/
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/* ptr to current */
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lis r2,init_task@h
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ori r2,r2,init_task@l
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/* ptr to current thread */
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addi r4,r2,THREAD /* init task's THREAD */
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mtspr SPRN_SPRG3,r4
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/* stack */
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lis r1,init_thread_union@h
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ori r1,r1,init_thread_union@l
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li r0,0
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stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
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bl early_init
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/*
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* Decide what sort of machine this is and initialize the MMU.
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*/
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mr r3,r31
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mr r4,r30
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mr r5,r29
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mr r6,r28
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mr r7,r27
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bl machine_init
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bl MMU_init
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/* Setup PTE pointers for the Abatron bdiGDB */
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lis r6, swapper_pg_dir@h
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ori r6, r6, swapper_pg_dir@l
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lis r5, abatron_pteptrs@h
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ori r5, r5, abatron_pteptrs@l
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lis r4, KERNELBASE@h
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ori r4, r4, KERNELBASE@l
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stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
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stw r6, 0(r5)
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/* Let's move on */
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lis r4,start_kernel@h
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ori r4,r4,start_kernel@l
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lis r3,MSR_KERNEL@h
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ori r3,r3,MSR_KERNEL@l
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mtspr SPRN_SRR0,r4
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mtspr SPRN_SRR1,r3
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rfi /* change context and jump to start_kernel */
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/*
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* Interrupt vector entry code
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*
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* The Book E MMUs are always on so we don't need to handle
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* interrupts in real mode as with previous PPC processors. In
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* this case we handle interrupts in the kernel virtual address
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* space.
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*
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* Interrupt vectors are dynamically placed relative to the
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* interrupt prefix as determined by the address of interrupt_base.
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* The interrupt vectors offsets are programmed using the labels
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* for each interrupt vector entry.
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*
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* Interrupt vectors must be aligned on a 16 byte boundary.
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* We align on a 32 byte cache line boundary for good measure.
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*/
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interrupt_base:
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/* Critical Input Interrupt */
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CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
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/* Machine Check Interrupt */
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CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
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MCHECK_EXCEPTION(0x0210, MachineCheckA, machine_check_exception)
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/* Data Storage Interrupt */
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START_EXCEPTION(DataStorage)
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mtspr SPRN_SPRG0, r10 /* Save some working registers */
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mtspr SPRN_SPRG1, r11
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mtspr SPRN_SPRG4W, r12
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mtspr SPRN_SPRG5W, r13
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mfcr r11
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mtspr SPRN_SPRG7W, r11
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/*
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* Check if it was a store fault, if not then bail
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* because a user tried to access a kernel or
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* read-protected page. Otherwise, get the
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* offending address and handle it.
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*/
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mfspr r10, SPRN_ESR
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andis. r10, r10, ESR_ST@h
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beq 2f
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mfspr r10, SPRN_DEAR /* Get faulting address */
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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*/
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lis r11, PAGE_OFFSET@h
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cmplw r10, r11
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blt+ 3f
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lis r11, swapper_pg_dir@h
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ori r11, r11, swapper_pg_dir@l
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mfspr r12,SPRN_MMUCR
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rlwinm r12,r12,0,0,23 /* Clear TID */
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b 4f
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/* Get the PGD for the current thread */
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3:
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mfspr r11,SPRN_SPRG3
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lwz r11,PGDIR(r11)
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/* Load PID into MMUCR TID */
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mfspr r12,SPRN_MMUCR /* Get MMUCR */
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mfspr r13,SPRN_PID /* Get PID */
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rlwimi r12,r13,0,24,31 /* Set TID */
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4:
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mtspr SPRN_MMUCR,r12
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rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
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lwzx r11, r12, r11 /* Get pgd/pmd entry */
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rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
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beq 2f /* Bail if no table */
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rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
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lwz r11, 4(r12) /* Get pte entry */
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andi. r13, r11, _PAGE_RW /* Is it writeable? */
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beq 2f /* Bail if not */
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/* Update 'changed'.
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*/
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ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
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stw r11, 4(r12) /* Update Linux page table */
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li r13, PPC44x_TLB_SR@l /* Set SR */
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rlwimi r13, r11, 29, 29, 29 /* SX = _PAGE_HWEXEC */
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rlwimi r13, r11, 0, 30, 30 /* SW = _PAGE_RW */
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rlwimi r13, r11, 29, 28, 28 /* UR = _PAGE_USER */
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rlwimi r12, r11, 31, 26, 26 /* (_PAGE_USER>>1)->r12 */
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rlwimi r12, r11, 29, 30, 30 /* (_PAGE_USER>>3)->r12 */
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and r12, r12, r11 /* HWEXEC/RW & USER */
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rlwimi r13, r12, 0, 26, 26 /* UX = HWEXEC & USER */
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rlwimi r13, r12, 3, 27, 27 /* UW = RW & USER */
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rlwimi r11,r13,0,26,31 /* Insert static perms */
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rlwinm r11,r11,0,20,15 /* Clear U0-U3 */
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/* find the TLB index that caused the fault. It has to be here. */
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tlbsx r10, 0, r10
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tlbwe r11, r10, PPC44x_TLB_ATTRIB /* Write ATTRIB */
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/* Done...restore registers and get out of here.
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*/
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mfspr r11, SPRN_SPRG7R
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mtcr r11
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mfspr r13, SPRN_SPRG5R
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mfspr r12, SPRN_SPRG4R
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mfspr r11, SPRN_SPRG1
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mfspr r10, SPRN_SPRG0
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rfi /* Force context change */
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2:
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/*
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* The bailout. Restore registers to pre-exception conditions
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* and call the heavyweights to help us out.
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*/
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mfspr r11, SPRN_SPRG7R
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mtcr r11
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mfspr r13, SPRN_SPRG5R
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mfspr r12, SPRN_SPRG4R
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mfspr r11, SPRN_SPRG1
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mfspr r10, SPRN_SPRG0
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b data_access
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/* Instruction Storage Interrupt */
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INSTRUCTION_STORAGE_EXCEPTION
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/* External Input Interrupt */
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EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
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/* Alignment Interrupt */
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ALIGNMENT_EXCEPTION
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/* Program Interrupt */
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PROGRAM_EXCEPTION
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|
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/* Floating Point Unavailable Interrupt */
|
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#ifdef CONFIG_PPC_FPU
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FP_UNAVAILABLE_EXCEPTION
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#else
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EXCEPTION(0x2010, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
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#endif
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/* System Call Interrupt */
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START_EXCEPTION(SystemCall)
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NORMAL_EXCEPTION_PROLOG
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EXC_XFER_EE_LITE(0x0c00, DoSyscall)
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/* Auxillary Processor Unavailable Interrupt */
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EXCEPTION(0x2020, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
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|
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/* Decrementer Interrupt */
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DECREMENTER_EXCEPTION
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|
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/* Fixed Internal Timer Interrupt */
|
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/* TODO: Add FIT support */
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EXCEPTION(0x1010, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
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|
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/* Watchdog Timer Interrupt */
|
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/* TODO: Add watchdog support */
|
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#ifdef CONFIG_BOOKE_WDT
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CRITICAL_EXCEPTION(0x1020, WatchdogTimer, WatchdogException)
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#else
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CRITICAL_EXCEPTION(0x1020, WatchdogTimer, unknown_exception)
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#endif
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|
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/* Data TLB Error Interrupt */
|
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START_EXCEPTION(DataTLBError)
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mtspr SPRN_SPRG0, r10 /* Save some working registers */
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mtspr SPRN_SPRG1, r11
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mtspr SPRN_SPRG4W, r12
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mtspr SPRN_SPRG5W, r13
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mfcr r11
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mtspr SPRN_SPRG7W, r11
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mfspr r10, SPRN_DEAR /* Get faulting address */
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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*/
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lis r11, PAGE_OFFSET@h
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cmplw r10, r11
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blt+ 3f
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lis r11, swapper_pg_dir@h
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ori r11, r11, swapper_pg_dir@l
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mfspr r12,SPRN_MMUCR
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rlwinm r12,r12,0,0,23 /* Clear TID */
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b 4f
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/* Get the PGD for the current thread */
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3:
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mfspr r11,SPRN_SPRG3
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lwz r11,PGDIR(r11)
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/* Load PID into MMUCR TID */
|
|
mfspr r12,SPRN_MMUCR
|
|
mfspr r13,SPRN_PID /* Get PID */
|
|
rlwimi r12,r13,0,24,31 /* Set TID */
|
|
|
|
4:
|
|
mtspr SPRN_MMUCR,r12
|
|
|
|
rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
|
|
lwzx r11, r12, r11 /* Get pgd/pmd entry */
|
|
rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
|
|
beq 2f /* Bail if no table */
|
|
|
|
rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
|
|
lwz r11, 4(r12) /* Get pte entry */
|
|
andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
|
|
beq 2f /* Bail if not present */
|
|
|
|
ori r11, r11, _PAGE_ACCESSED
|
|
stw r11, 4(r12)
|
|
|
|
/* Jump to common tlb load */
|
|
b finish_tlb_load
|
|
|
|
2:
|
|
/* The bailout. Restore registers to pre-exception conditions
|
|
* and call the heavyweights to help us out.
|
|
*/
|
|
mfspr r11, SPRN_SPRG7R
|
|
mtcr r11
|
|
mfspr r13, SPRN_SPRG5R
|
|
mfspr r12, SPRN_SPRG4R
|
|
mfspr r11, SPRN_SPRG1
|
|
mfspr r10, SPRN_SPRG0
|
|
b data_access
|
|
|
|
/* Instruction TLB Error Interrupt */
|
|
/*
|
|
* Nearly the same as above, except we get our
|
|
* information from different registers and bailout
|
|
* to a different point.
|
|
*/
|
|
START_EXCEPTION(InstructionTLBError)
|
|
mtspr SPRN_SPRG0, r10 /* Save some working registers */
|
|
mtspr SPRN_SPRG1, r11
|
|
mtspr SPRN_SPRG4W, r12
|
|
mtspr SPRN_SPRG5W, r13
|
|
mfcr r11
|
|
mtspr SPRN_SPRG7W, r11
|
|
mfspr r10, SPRN_SRR0 /* Get faulting address */
|
|
|
|
/* If we are faulting a kernel address, we have to use the
|
|
* kernel page tables.
|
|
*/
|
|
lis r11, PAGE_OFFSET@h
|
|
cmplw r10, r11
|
|
blt+ 3f
|
|
lis r11, swapper_pg_dir@h
|
|
ori r11, r11, swapper_pg_dir@l
|
|
|
|
mfspr r12,SPRN_MMUCR
|
|
rlwinm r12,r12,0,0,23 /* Clear TID */
|
|
|
|
b 4f
|
|
|
|
/* Get the PGD for the current thread */
|
|
3:
|
|
mfspr r11,SPRN_SPRG3
|
|
lwz r11,PGDIR(r11)
|
|
|
|
/* Load PID into MMUCR TID */
|
|
mfspr r12,SPRN_MMUCR
|
|
mfspr r13,SPRN_PID /* Get PID */
|
|
rlwimi r12,r13,0,24,31 /* Set TID */
|
|
|
|
4:
|
|
mtspr SPRN_MMUCR,r12
|
|
|
|
rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */
|
|
lwzx r11, r12, r11 /* Get pgd/pmd entry */
|
|
rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */
|
|
beq 2f /* Bail if no table */
|
|
|
|
rlwimi r12, r10, 23, 20, 28 /* Compute pte address */
|
|
lwz r11, 4(r12) /* Get pte entry */
|
|
andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
|
|
beq 2f /* Bail if not present */
|
|
|
|
ori r11, r11, _PAGE_ACCESSED
|
|
stw r11, 4(r12)
|
|
|
|
/* Jump to common TLB load point */
|
|
b finish_tlb_load
|
|
|
|
2:
|
|
/* The bailout. Restore registers to pre-exception conditions
|
|
* and call the heavyweights to help us out.
|
|
*/
|
|
mfspr r11, SPRN_SPRG7R
|
|
mtcr r11
|
|
mfspr r13, SPRN_SPRG5R
|
|
mfspr r12, SPRN_SPRG4R
|
|
mfspr r11, SPRN_SPRG1
|
|
mfspr r10, SPRN_SPRG0
|
|
b InstructionStorage
|
|
|
|
/* Debug Interrupt */
|
|
DEBUG_CRIT_EXCEPTION
|
|
|
|
/*
|
|
* Local functions
|
|
*/
|
|
/*
|
|
* Data TLB exceptions will bail out to this point
|
|
* if they can't resolve the lightweight TLB fault.
|
|
*/
|
|
data_access:
|
|
NORMAL_EXCEPTION_PROLOG
|
|
mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
|
|
stw r5,_ESR(r11)
|
|
mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
|
|
EXC_XFER_EE_LITE(0x0300, handle_page_fault)
|
|
|
|
/*
|
|
|
|
* Both the instruction and data TLB miss get to this
|
|
* point to load the TLB.
|
|
* r10 - EA of fault
|
|
* r11 - available to use
|
|
* r12 - Pointer to the 64-bit PTE
|
|
* r13 - available to use
|
|
* MMUCR - loaded with proper value when we get here
|
|
* Upon exit, we reload everything and RFI.
|
|
*/
|
|
finish_tlb_load:
|
|
/*
|
|
* We set execute, because we don't have the granularity to
|
|
* properly set this at the page level (Linux problem).
|
|
* If shared is set, we cause a zero PID->TID load.
|
|
* Many of these bits are software only. Bits we don't set
|
|
* here we (properly should) assume have the appropriate value.
|
|
*/
|
|
|
|
/* Load the next available TLB index */
|
|
lis r13, tlb_44x_index@ha
|
|
lwz r13, tlb_44x_index@l(r13)
|
|
/* Load the TLB high watermark */
|
|
lis r11, tlb_44x_hwater@ha
|
|
lwz r11, tlb_44x_hwater@l(r11)
|
|
|
|
/* Increment, rollover, and store TLB index */
|
|
addi r13, r13, 1
|
|
cmpw 0, r13, r11 /* reserve entries */
|
|
ble 7f
|
|
li r13, 0
|
|
7:
|
|
/* Store the next available TLB index */
|
|
lis r11, tlb_44x_index@ha
|
|
stw r13, tlb_44x_index@l(r11)
|
|
|
|
lwz r11, 0(r12) /* Get MS word of PTE */
|
|
lwz r12, 4(r12) /* Get LS word of PTE */
|
|
rlwimi r11, r12, 0, 0 , 19 /* Insert RPN */
|
|
tlbwe r11, r13, PPC44x_TLB_XLAT /* Write XLAT */
|
|
|
|
/*
|
|
* Create PAGEID. This is the faulting address,
|
|
* page size, and valid flag.
|
|
*/
|
|
li r11, PPC44x_TLB_VALID | PPC44x_TLB_4K
|
|
rlwimi r10, r11, 0, 20, 31 /* Insert valid and page size */
|
|
tlbwe r10, r13, PPC44x_TLB_PAGEID /* Write PAGEID */
|
|
|
|
li r10, PPC44x_TLB_SR@l /* Set SR */
|
|
rlwimi r10, r12, 0, 30, 30 /* Set SW = _PAGE_RW */
|
|
rlwimi r10, r12, 29, 29, 29 /* SX = _PAGE_HWEXEC */
|
|
rlwimi r10, r12, 29, 28, 28 /* UR = _PAGE_USER */
|
|
rlwimi r11, r12, 31, 26, 26 /* (_PAGE_USER>>1)->r12 */
|
|
and r11, r12, r11 /* HWEXEC & USER */
|
|
rlwimi r10, r11, 0, 26, 26 /* UX = HWEXEC & USER */
|
|
|
|
rlwimi r12, r10, 0, 26, 31 /* Insert static perms */
|
|
rlwinm r12, r12, 0, 20, 15 /* Clear U0-U3 */
|
|
tlbwe r12, r13, PPC44x_TLB_ATTRIB /* Write ATTRIB */
|
|
|
|
/* Done...restore registers and get out of here.
|
|
*/
|
|
mfspr r11, SPRN_SPRG7R
|
|
mtcr r11
|
|
mfspr r13, SPRN_SPRG5R
|
|
mfspr r12, SPRN_SPRG4R
|
|
mfspr r11, SPRN_SPRG1
|
|
mfspr r10, SPRN_SPRG0
|
|
rfi /* Force context change */
|
|
|
|
/*
|
|
* Global functions
|
|
*/
|
|
|
|
/*
|
|
* Adjust the machine check IVOR on 440A cores
|
|
*/
|
|
_GLOBAL(__fixup_440A_mcheck)
|
|
li r3,MachineCheckA@l
|
|
mtspr SPRN_IVOR1,r3
|
|
sync
|
|
blr
|
|
|
|
/*
|
|
* extern void giveup_altivec(struct task_struct *prev)
|
|
*
|
|
* The 44x core does not have an AltiVec unit.
|
|
*/
|
|
_GLOBAL(giveup_altivec)
|
|
blr
|
|
|
|
/*
|
|
* extern void giveup_fpu(struct task_struct *prev)
|
|
*
|
|
* The 44x core does not have an FPU.
|
|
*/
|
|
#ifndef CONFIG_PPC_FPU
|
|
_GLOBAL(giveup_fpu)
|
|
blr
|
|
#endif
|
|
|
|
_GLOBAL(set_context)
|
|
|
|
#ifdef CONFIG_BDI_SWITCH
|
|
/* Context switch the PTE pointer for the Abatron BDI2000.
|
|
* The PGDIR is the second parameter.
|
|
*/
|
|
lis r5, abatron_pteptrs@h
|
|
ori r5, r5, abatron_pteptrs@l
|
|
stw r4, 0x4(r5)
|
|
#endif
|
|
mtspr SPRN_PID,r3
|
|
isync /* Force context change */
|
|
blr
|
|
|
|
/*
|
|
* We put a few things here that have to be page-aligned. This stuff
|
|
* goes at the beginning of the data segment, which is page-aligned.
|
|
*/
|
|
.data
|
|
.align 12
|
|
.globl sdata
|
|
sdata:
|
|
.globl empty_zero_page
|
|
empty_zero_page:
|
|
.space 4096
|
|
|
|
/*
|
|
* To support >32-bit physical addresses, we use an 8KB pgdir.
|
|
*/
|
|
.globl swapper_pg_dir
|
|
swapper_pg_dir:
|
|
.space PGD_TABLE_SIZE
|
|
|
|
/* Reserved 4k for the critical exception stack & 4k for the machine
|
|
* check stack per CPU for kernel mode exceptions */
|
|
.section .bss
|
|
.align 12
|
|
exception_stack_bottom:
|
|
.space BOOKE_EXCEPTION_STACK_SIZE
|
|
.globl exception_stack_top
|
|
exception_stack_top:
|
|
|
|
/*
|
|
* Room for two PTE pointers, usually the kernel and current user pointers
|
|
* to their respective root page table.
|
|
*/
|
|
abatron_pteptrs:
|
|
.space 8
|