1aafd90912
revise anomaly handling by basing things on the compiler not the kconfig defines, so the header is stable and usable outside of the kernel. This also allows us to move some code from preprocessing to compiling (gcc culls dead code) which should help with code quality (readability, catch minor bugs, etc...). Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
77 lines
2 KiB
ArmAsm
77 lines
2 KiB
ArmAsm
/*
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* File: arch/blackfin/mach-common/cacheinit.S
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* Based on:
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* Author: LG Soft India
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*
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* Created: ?
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* Description: cache initialization
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*
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* Modified:
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* Copyright 2004-2006 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* This function sets up the data and instruction cache. The
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* tables like icplb table, dcplb table and Page Descriptor table
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* are defined in cplbtab.h. You can configure those tables for
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* your suitable requirements
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*/
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#include <linux/linkage.h>
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#include <asm/blackfin.h>
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.text
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#if ANOMALY_05000125
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#if defined(CONFIG_BLKFIN_CACHE)
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ENTRY(_bfin_write_IMEM_CONTROL)
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/* Enable Instruction Cache */
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P0.l = (IMEM_CONTROL & 0xFFFF);
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P0.h = (IMEM_CONTROL >> 16);
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/* Anomaly 05000125 */
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CLI R1;
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SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
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.align 8;
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[P0] = R0;
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SSYNC;
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STI R1;
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RTS;
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ENDPROC(_bfin_write_IMEM_CONTROL)
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#endif
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#if defined(CONFIG_BLKFIN_DCACHE)
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ENTRY(_bfin_write_DMEM_CONTROL)
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P0.l = (DMEM_CONTROL & 0xFFFF);
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P0.h = (DMEM_CONTROL >> 16);
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CLI R1;
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SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
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.align 8;
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[P0] = R0;
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SSYNC;
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STI R1;
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RTS;
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ENDPROC(_bfin_write_DMEM_CONTROL)
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#endif
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#endif
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