820d41cf0c
Rob Herring has done a sweeping change cleaning up all of the mach/io.h includes, moving some of the oft-repeated macros to a common location and removing a bunch of boiler plate. This is another step closer to a common zImage for multiple platforms. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJPcpqHAAoJEIwa5zzehBx3xCMP/2evrPQyorzMBztrFB4Ry9Ol qNkSVNsemZjdtkY2dnJv+zJ/Xb0PPDU9EuBHr/SpqmVrRZEZeJND42wZK/OTFCBZ Ufi7KP1qE30daO5H3YmL+58/Ixir5fTHqggqolHhTcEYU2hnHgLBI4rIFu92kSO7 TMyrAUs14jSkTVZc6HSF83w3PfQWhMzWvspJVHQ6RebZRruETAr7v9weVMbgxcDk jQ5XJ9y73rGs2AF8bZTpUdFPzkcac7UiHn3/XyqoZs8RNCL98BGpskzhILyTARf5 X90c9mqQF+AEbb9QSDDd52uYFsJ/5COJvWdlExRI9gZZDI8Pd05ijZBR9IdGJg/B NsVsl98wvZ/zjHJ/Sb2qt5ruet7PiQUGhkshB42jVHsaWfRM030sKGYxQ8pX5Tsa cSagnfBCvAZ9VjDLkXrnEbWRNTz8LSwn9l63z0jmtm5D8+vbpMtgvtWARtuZ4RNn D8wIWoyT0ytVZnosu5441TEgCejtcKOEFzThvKDYMeMJZ/rqVkAbcznapoC2qUd4 fceNlLfQFvW7xpY1MY8mhlwC0ki4hM9MSDieaXUyefvAU/hoSp8MveVUH5UspYfb 0FpkEhzklW/g0/fuq0DJQIrMn7dajjUvVZIUQtiVQuFHOr6RUbFG5vmXuCbAyx10 PE2K4rnKz+PC8bKab7v9 =YIsn -----END PGP SIGNATURE----- Merge tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull "ARM: cleanups of io includes" from Olof Johansson: "Rob Herring has done a sweeping change cleaning up all of the mach/io.h includes, moving some of the oft-repeated macros to a common location and removing a bunch of boiler plate. This is another step closer to a common zImage for multiple platforms." Fix up various fairly trivial conflicts (<mach/io.h> removal vs changes around it, tegra localtimer.o is *still* gone, yadda-yadda). * tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (29 commits) ARM: tegra: Include assembler.h in sleep.S to fix build break ARM: pxa: use common IOMEM definition ARM: dma-mapping: convert ARCH_HAS_DMA_SET_COHERENT_MASK to kconfig symbol ARM: __io abuse cleanup ARM: create a common IOMEM definition ARM: iop13xx: fix missing declaration of iop13xx_init_early ARM: fix ioremap/iounmap for !CONFIG_MMU ARM: kill off __mem_pci ARM: remove bunch of now unused mach/io.h files ARM: make mach/io.h include optional ARM: clps711x: remove unneeded include of mach/io.h ARM: dove: add explicit include of dove.h to addr-map.c ARM: at91: add explicit include of hardware.h to uncompressor ARM: ep93xx: clean-up mach/io.h ARM: tegra: clean-up mach/io.h ARM: orion5x: clean-up mach/io.h ARM: davinci: remove unneeded mach/io.h include [media] davinci: remove includes of mach/io.h ARM: OMAP: Remove remaining includes for mach/io.h ARM: msm: clean-up mach/io.h ...
323 lines
6.8 KiB
C
323 lines
6.8 KiB
C
/*
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* arch/arm/include/asm/assembler.h
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*
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* Copyright (C) 1996-2000 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This file contains arm architecture specific defines
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* for the different processors.
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*
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* Do not include any C declarations in this file - it is included by
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* assembler source.
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*/
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#ifndef __ASM_ASSEMBLER_H__
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#define __ASM_ASSEMBLER_H__
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#ifndef __ASSEMBLY__
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#error "Only include this from assembly code"
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#endif
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#include <asm/ptrace.h>
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#include <asm/domain.h>
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#define IOMEM(x) (x)
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/*
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* Endian independent macros for shifting bytes within registers.
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*/
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#ifndef __ARMEB__
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#define pull lsr
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#define push lsl
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#define get_byte_0 lsl #0
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#define get_byte_1 lsr #8
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#define get_byte_2 lsr #16
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#define get_byte_3 lsr #24
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#define put_byte_0 lsl #0
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#define put_byte_1 lsl #8
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#define put_byte_2 lsl #16
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#define put_byte_3 lsl #24
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#else
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#define pull lsl
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#define push lsr
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#define get_byte_0 lsr #24
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#define get_byte_1 lsr #16
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#define get_byte_2 lsr #8
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#define get_byte_3 lsl #0
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#define put_byte_0 lsl #24
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#define put_byte_1 lsl #16
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#define put_byte_2 lsl #8
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#define put_byte_3 lsl #0
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#endif
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/*
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* Data preload for architectures that support it
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*/
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#if __LINUX_ARM_ARCH__ >= 5
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#define PLD(code...) code
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#else
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#define PLD(code...)
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#endif
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/*
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* This can be used to enable code to cacheline align the destination
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* pointer when bulk writing to memory. Experiments on StrongARM and
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* XScale didn't show this a worthwhile thing to do when the cache is not
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* set to write-allocate (this would need further testing on XScale when WA
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* is used).
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*
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* On Feroceon there is much to gain however, regardless of cache mode.
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*/
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#ifdef CONFIG_CPU_FEROCEON
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#define CALGN(code...) code
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#else
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#define CALGN(code...)
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#endif
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/*
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* Enable and disable interrupts
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*/
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#if __LINUX_ARM_ARCH__ >= 6
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.macro disable_irq_notrace
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cpsid i
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.endm
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.macro enable_irq_notrace
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cpsie i
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.endm
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#else
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.macro disable_irq_notrace
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msr cpsr_c, #PSR_I_BIT | SVC_MODE
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.endm
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.macro enable_irq_notrace
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msr cpsr_c, #SVC_MODE
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.endm
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#endif
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.macro asm_trace_hardirqs_off
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#if defined(CONFIG_TRACE_IRQFLAGS)
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stmdb sp!, {r0-r3, ip, lr}
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bl trace_hardirqs_off
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ldmia sp!, {r0-r3, ip, lr}
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#endif
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.endm
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.macro asm_trace_hardirqs_on_cond, cond
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#if defined(CONFIG_TRACE_IRQFLAGS)
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/*
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* actually the registers should be pushed and pop'd conditionally, but
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* after bl the flags are certainly clobbered
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*/
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stmdb sp!, {r0-r3, ip, lr}
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bl\cond trace_hardirqs_on
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ldmia sp!, {r0-r3, ip, lr}
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#endif
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.endm
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.macro asm_trace_hardirqs_on
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asm_trace_hardirqs_on_cond al
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.endm
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.macro disable_irq
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disable_irq_notrace
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asm_trace_hardirqs_off
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.endm
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.macro enable_irq
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asm_trace_hardirqs_on
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enable_irq_notrace
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.endm
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/*
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* Save the current IRQ state and disable IRQs. Note that this macro
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* assumes FIQs are enabled, and that the processor is in SVC mode.
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*/
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.macro save_and_disable_irqs, oldcpsr
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mrs \oldcpsr, cpsr
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disable_irq
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.endm
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.macro save_and_disable_irqs_notrace, oldcpsr
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mrs \oldcpsr, cpsr
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disable_irq_notrace
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.endm
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/*
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* Restore interrupt state previously stored in a register. We don't
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* guarantee that this will preserve the flags.
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*/
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.macro restore_irqs_notrace, oldcpsr
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msr cpsr_c, \oldcpsr
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.endm
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.macro restore_irqs, oldcpsr
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tst \oldcpsr, #PSR_I_BIT
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asm_trace_hardirqs_on_cond eq
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restore_irqs_notrace \oldcpsr
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.endm
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#define USER(x...) \
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9999: x; \
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.pushsection __ex_table,"a"; \
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.align 3; \
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.long 9999b,9001f; \
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.popsection
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#ifdef CONFIG_SMP
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#define ALT_SMP(instr...) \
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9998: instr
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/*
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* Note: if you get assembler errors from ALT_UP() when building with
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* CONFIG_THUMB2_KERNEL, you almost certainly need to use
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* ALT_SMP( W(instr) ... )
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*/
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#define ALT_UP(instr...) \
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.pushsection ".alt.smp.init", "a" ;\
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.long 9998b ;\
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9997: instr ;\
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.if . - 9997b != 4 ;\
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.error "ALT_UP() content must assemble to exactly 4 bytes";\
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.endif ;\
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.popsection
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#define ALT_UP_B(label) \
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.equ up_b_offset, label - 9998b ;\
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.pushsection ".alt.smp.init", "a" ;\
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.long 9998b ;\
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W(b) . + up_b_offset ;\
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.popsection
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#else
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#define ALT_SMP(instr...)
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#define ALT_UP(instr...) instr
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#define ALT_UP_B(label) b label
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#endif
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/*
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* Instruction barrier
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*/
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.macro instr_sync
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#if __LINUX_ARM_ARCH__ >= 7
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isb
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#elif __LINUX_ARM_ARCH__ == 6
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mcr p15, 0, r0, c7, c5, 4
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#endif
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.endm
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/*
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* SMP data memory barrier
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*/
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.macro smp_dmb mode
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#ifdef CONFIG_SMP
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#if __LINUX_ARM_ARCH__ >= 7
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.ifeqs "\mode","arm"
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ALT_SMP(dmb)
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.else
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ALT_SMP(W(dmb))
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.endif
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#elif __LINUX_ARM_ARCH__ == 6
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ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
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#else
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#error Incompatible SMP platform
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#endif
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.ifeqs "\mode","arm"
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ALT_UP(nop)
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.else
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ALT_UP(W(nop))
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.endif
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#endif
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.endm
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#ifdef CONFIG_THUMB2_KERNEL
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.macro setmode, mode, reg
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mov \reg, #\mode
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msr cpsr_c, \reg
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.endm
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#else
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.macro setmode, mode, reg
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msr cpsr_c, #\mode
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.endm
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#endif
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/*
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* STRT/LDRT access macros with ARM and Thumb-2 variants
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*/
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#ifdef CONFIG_THUMB2_KERNEL
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.macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
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9999:
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.if \inc == 1
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\instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
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.elseif \inc == 4
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\instr\cond\()\t\().w \reg, [\ptr, #\off]
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.else
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.error "Unsupported inc macro argument"
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.endif
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.pushsection __ex_table,"a"
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.align 3
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.long 9999b, \abort
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.popsection
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.endm
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.macro usracc, instr, reg, ptr, inc, cond, rept, abort
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@ explicit IT instruction needed because of the label
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@ introduced by the USER macro
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.ifnc \cond,al
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.if \rept == 1
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itt \cond
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.elseif \rept == 2
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ittt \cond
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.else
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.error "Unsupported rept macro argument"
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.endif
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.endif
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@ Slightly optimised to avoid incrementing the pointer twice
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usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
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.if \rept == 2
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usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
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.endif
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add\cond \ptr, #\rept * \inc
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.endm
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#else /* !CONFIG_THUMB2_KERNEL */
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.macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
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.rept \rept
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9999:
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.if \inc == 1
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\instr\cond\()b\()\t \reg, [\ptr], #\inc
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.elseif \inc == 4
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\instr\cond\()\t \reg, [\ptr], #\inc
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.else
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.error "Unsupported inc macro argument"
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.endif
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.pushsection __ex_table,"a"
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.align 3
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.long 9999b, \abort
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.popsection
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.endr
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.endm
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#endif /* CONFIG_THUMB2_KERNEL */
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.macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
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usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
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.endm
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.macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
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usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
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.endm
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/* Utility macro for declaring string literals */
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.macro string name:req, string
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.type \name , #object
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\name:
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.asciz "\string"
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.size \name , . - \name
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.endm
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#endif /* __ASM_ASSEMBLER_H__ */
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