c53c9cf60e
Add core support for the Kendin/Micrel KS8695 processor family. It is an ARM922-T based SoC with integrated USART, 4-port Ethernet Switch, WAN Ethernet port, and optional PCI Host bridge, etc. http://www.micrel.com/page.do?page=product-info/sys_on_chip.jsp This patch is based on earlier patches from Lennert Buytenhek, Ben Dooks and Greg Ungerer posted to the arm-linux-kernel mailing list in March 2006; and Micrel's 2.6.9 port. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
66 lines
2.3 KiB
C
66 lines
2.3 KiB
C
/*
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* include/asm-arm/arch-ks8695/regs-switch.h
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*
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* Copyright (C) 2006 Andrew Victor
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*
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* KS8695 - Switch Registers and bit definitions.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef KS8695_SWITCH_H
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#define KS8695_SWITCH_H
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#define KS8695_SWITCH_OFFSET (0xF0000 + 0xe800)
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#define KS8695_SWITCH_VA (KS8695_IO_VA + KS8695_SWITCH_OFFSET)
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#define KS8695_SWITCH_PA (KS8695_IO_PA + KS8695_SWITCH_OFFSET)
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/*
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* Switch registers
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*/
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#define KS8695_SEC0 (0x00) /* Switch Engine Control 0 */
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#define KS8695_SEC1 (0x04) /* Switch Engine Control 1 */
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#define KS8695_SEC2 (0x08) /* Switch Engine Control 2 */
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#define KS8695_P(x)_C(z) (0xc0 + (((x)-1)*3 + ((z)-1))*4) /* Port Configuration Registers */
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#define KS8695_SEP12AN (0x48) /* Port 1 & 2 Auto-Negotiation */
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#define KS8695_SEP34AN (0x4c) /* Port 3 & 4 Auto-Negotiation */
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#define KS8695_SEIAC (0x50) /* Indirect Access Control */
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#define KS8695_SEIADH2 (0x54) /* Indirect Access Data High 2 */
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#define KS8695_SEIADH1 (0x58) /* Indirect Access Data High 1 */
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#define KS8695_SEIADL (0x5c) /* Indirect Access Data Low */
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#define KS8695_SEAFC (0x60) /* Advance Feature Control */
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#define KS8695_SEDSCPH (0x64) /* TOS Priority High */
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#define KS8695_SEDSCPL (0x68) /* TOS Priority Low */
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#define KS8695_SEMAH (0x6c) /* Switch Engine MAC Address High */
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#define KS8695_SEMAL (0x70) /* Switch Engine MAC Address Low */
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#define KS8695_LPPM12 (0x74) /* Port 1 & 2 PHY Power Management */
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#define KS8695_LPPM34 (0x78) /* Port 3 & 4 PHY Power Management */
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/* Switch Engine Control 0 */
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#define SEC0_LLED1S (7 << 25) /* LED1 Select */
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#define LLED1S_SPEED (0 << 25)
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#define LLED1S_LINK (1 << 25)
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#define LLED1S_DUPLEX (2 << 25)
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#define LLED1S_COLLISION (3 << 25)
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#define LLED1S_ACTIVITY (4 << 25)
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#define LLED1S_FDX_COLLISION (5 << 25)
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#define LLED1S_LINK_ACTIVITY (6 << 25)
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#define SEC0_LLED0S (7 << 22) /* LED0 Select */
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#define LLED0S_SPEED (0 << 22)
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#define LLED0S_LINK (1 << 22)
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#define LLED0S_DUPLEX (2 << 22)
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#define LLED0S_COLLISION (3 << 22)
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#define LLED0S_ACTIVITY (4 << 22)
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#define LLED0S_FDX_COLLISION (5 << 22)
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#define LLED0S_LINK_ACTIVITY (6 << 22)
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#define SEC0_ENABLE (1 << 0) /* Enable Switch */
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#endif
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