kernel-fxtec-pro1x/Documentation/arm64
James Morse 1b568dfec3 arm64: errata: Hide CTR_EL0.DIC on systems affected by Neoverse-N1 #1542419
[ Upstream commit 05460849c3b51180d5ada3373d0449aea19075e4 ]

Cores affected by Neoverse-N1 #1542419 could execute a stale instruction
when a branch is updated to point to freshly generated instructions.

To workaround this issue we need user-space to issue unnecessary
icache maintenance that we can trap. Start by hiding CTR_EL0.DIC.

Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
[ Removed cpu_enable_trap_ctr_access() hunk due to no 4afe8e79da92]
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-04-29 16:31:08 +02:00
..
acpi_object_usage.txt
arm-acpi.txt
booting.txt
cpu-feature-registers.txt
elf_hwcaps.txt arm64: docs: Document SSBS HWCAP 2019-10-11 18:21:31 +02:00
legacy_instructions.txt
memory.txt
silicon-errata.txt arm64: errata: Hide CTR_EL0.DIC on systems affected by Neoverse-N1 #1542419 2020-04-29 16:31:08 +02:00
sve.txt
tagged-pointers.txt