e344b63eee
The attached patches provides part 7 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
155 lines
4.5 KiB
C
155 lines
4.5 KiB
C
#ifndef _uart_h_included_
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#define _uart_h_included_
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/*
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* THIS FILE IS GENERATED -- DO NOT MODIFY BY HAND
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*
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* include/asm-xtensa/xtensa/xt2000-uart.h -- NatSemi PC16552D DUART
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* definitions
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2002 Tensilica Inc.
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*/
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#include <xtensa/xt2000.h>
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/* 16550 UART DEVICE REGISTERS
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The XT2000 board aligns each register to a 32-bit word but the UART device only uses
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one byte of the word, which is the least-significant byte regardless of the
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endianness of the core (ie. byte offset 0 for little-endian and 3 for big-endian).
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So if using word accesses then endianness doesn't matter.
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The macros provided here do that.
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*/
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struct uart_dev_s {
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union {
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unsigned int rxb; /* DLAB=0: receive buffer, read-only */
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unsigned int txb; /* DLAB=0: transmit buffer, write-only */
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unsigned int dll; /* DLAB=1: divisor, least-significant byte latch (was write-only?) */
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} w0;
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union {
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unsigned int ier; /* DLAB=0: interrupt-enable register (was write-only?) */
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unsigned int dlm; /* DLAB=1: divisor, most-significant byte latch (was write-only?) */
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} w1;
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union {
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unsigned int isr; /* DLAB=0: interrupt status register, read-only */
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unsigned int fcr; /* DLAB=0: FIFO control register, write-only */
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unsigned int afr; /* DLAB=1: alternate function register */
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} w2;
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unsigned int lcr; /* line control-register, write-only */
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unsigned int mcr; /* modem control-regsiter, write-only */
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unsigned int lsr; /* line status register, read-only */
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unsigned int msr; /* modem status register, read-only */
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unsigned int scr; /* scratch regsiter, read/write */
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};
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#define _RXB(u) ((u)->w0.rxb)
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#define _TXB(u) ((u)->w0.txb)
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#define _DLL(u) ((u)->w0.dll)
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#define _IER(u) ((u)->w1.ier)
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#define _DLM(u) ((u)->w1.dlm)
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#define _ISR(u) ((u)->w2.isr)
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#define _FCR(u) ((u)->w2.fcr)
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#define _AFR(u) ((u)->w2.afr)
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#define _LCR(u) ((u)->lcr)
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#define _MCR(u) ((u)->mcr)
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#define _LSR(u) ((u)->lsr)
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#define _MSR(u) ((u)->msr)
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#define _SCR(u) ((u)->scr)
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typedef volatile struct uart_dev_s uart_dev_t;
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/* IER bits */
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#define RCVR_DATA_REG_INTENABLE 0x01
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#define XMIT_HOLD_REG_INTENABLE 0x02
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#define RCVR_STATUS_INTENABLE 0x04
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#define MODEM_STATUS_INTENABLE 0x08
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/* FCR bits */
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#define _FIFO_ENABLE 0x01
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#define RCVR_FIFO_RESET 0x02
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#define XMIT_FIFO_RESET 0x04
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#define DMA_MODE_SELECT 0x08
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#define RCVR_TRIGGER_LSB 0x40
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#define RCVR_TRIGGER_MSB 0x80
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/* AFR bits */
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#define AFR_CONC_WRITE 0x01
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#define AFR_BAUDOUT_SEL 0x02
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#define AFR_RXRDY_SEL 0x04
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/* ISR bits */
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#define INT_STATUS(r) ((r)&1)
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#define INT_PRIORITY(r) (((r)>>1)&0x7)
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/* LCR bits */
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#define WORD_LENGTH(n) (((n)-5)&0x3)
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#define STOP_BIT_ENABLE 0x04
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#define PARITY_ENABLE 0x08
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#define EVEN_PARITY 0x10
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#define FORCE_PARITY 0x20
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#define XMIT_BREAK 0x40
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#define DLAB_ENABLE 0x80
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/* MCR bits */
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#define _DTR 0x01
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#define _RTS 0x02
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#define _OP1 0x04
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#define _OP2 0x08
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#define LOOP_BACK 0x10
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/* LSR Bits */
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#define RCVR_DATA_READY 0x01
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#define OVERRUN_ERROR 0x02
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#define PARITY_ERROR 0x04
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#define FRAMING_ERROR 0x08
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#define BREAK_INTERRUPT 0x10
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#define XMIT_HOLD_EMPTY 0x20
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#define XMIT_EMPTY 0x40
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#define FIFO_ERROR 0x80
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#define RCVR_READY(u) (_LSR(u)&RCVR_DATA_READY)
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#define XMIT_READY(u) (_LSR(u)&XMIT_HOLD_EMPTY)
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/* MSR bits */
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#define _RDR 0x01
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#define DELTA_DSR 0x02
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#define DELTA_RI 0x04
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#define DELTA_CD 0x08
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#define _CTS 0x10
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#define _DSR 0x20
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#define _RI 0x40
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#define _CD 0x80
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/* prototypes */
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void uart_init( uart_dev_t *u, int bitrate );
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void uart_out( uart_dev_t *u, char c );
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void uart_puts( uart_dev_t *u, char *s );
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char uart_in( uart_dev_t *u );
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void uart_enable_rcvr_int( uart_dev_t *u );
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void uart_disable_rcvr_int( uart_dev_t *u );
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#ifdef DUART16552_1_VADDR
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/* DUART present. */
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#define DUART_1_BASE (*(uart_dev_t*)DUART16552_1_VADDR)
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#define DUART_2_BASE (*(uart_dev_t*)DUART16552_2_VADDR)
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#define UART1_PUTS(s) uart_puts( &DUART_1_BASE, s )
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#define UART2_PUTS(s) uart_puts( &DUART_2_BASE, s )
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#else
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/* DUART not configured, use dummy placeholders to allow compiles to work. */
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#define DUART_1_BASE (*(uart_dev_t*)0)
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#define DUART_2_BASE (*(uart_dev_t*)0)
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#define UART1_PUTS(s)
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#define UART2_PUTS(s)
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#endif
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/* Compute 16-bit divisor for baudrate generator, with rounding: */
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#define DUART_DIVISOR(crystal,speed) (((crystal)/16 + (speed)/2)/(speed))
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#endif /*_uart_h_included_*/
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